Z8 PLZ/ASM. Assembly Language Programming Manual. December PDF

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Z8 PLZ/ASM Assembly Language Programming Manual December PLI/ASII Assembly Language ProgralDlDing lianual December 1980 Copyright 1980 by Zilog, Inc. All rights reserved. No part of this publication
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Z8 PLZ/ASM Assembly Language Programming Manual December 1980 18 PLI/ASII Assembly Language ProgralDlDing lianual December 1980 Copyright 1980 by Zilog, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of Zilog. Zilog assumes no responsibility for the use of any qircuitry other than circuitry embodied in a Zilog product. No other circuit patent licenses are implied. Preface This reference manual describes assembly language programming for Zilog's Z8 single-chip microcomputer. The first three sections of the manual focus on Z8 design features and the assembly-language instruction set. Sections 4 and 5 provide additional information needed to build a source program, including the use of high-level PLZ statements. This manual is one in a series describing the Z8. You will need several other manuals to develop, debug, and run Z8 assembly-language programs. Programs are developed on either Zilog's microcomputer system (MCZ) or the Zilog development system (ZDS) using the software capabilities of the RIO operating system. The manuals needed to use the operating system are: Z80 RIO Operating System User's Manual, Z80 RIO Text Editor User's Manual, The Z8 assembler produces relocatable object modules. Operation of the assembler and object module linkage and relocation are described in the: Z8 PLZ/ASM Assembler User Guide, PLZ Linker User Guide, Finally, while this programming manual includes an overview of the Z8 architecture, you will need the following manual for detailed hardware and configuration information: Z8 Microcomputer Technical Manual, iii Contents SECTION 1 ARCHITECTURAL OVERVIEW Introduction Memory Segments Program Memory.. External Data Memory Register Memory Da ta Leng ths Input/Output Port Port Port Port 3 Interrupts.... Timers/Counters Status Flags and Program Controls l-lc l-lc l-lc 1-1] 1-1~ Carry Flag Zero Flag Sign Flag Overflow Flag Decimal Adjust Flag Ha 1 f Ca r r y Fl ag 1-1; 1-1: 1-1: Stack Memory I-I! SECTION 2 Z8 ASSEMBLER CONVENTIONS Assembler Overview Assembly Language Statement Format Program Labels and Identifiers Instruction Operand Field Comments Arithmetic Operands Run-Time Versus Assembly-Time Ari thmetic Constants Data variables Expressions and Operators v CONTENTS (cont.) SECTION 2 Z8 ASSEMBLER CONVENTIONS (cont.) 2.4 Z8 Addressing Modes Reg ister Address Indirect-Register Address 2-15 Indexed Address Direct Address 2-17 Relative Address 2-17 Immediate Data A Note on the Register Pointer 2-19 SECTION 3 ASSEMBLY-LANGUAGE INSTRUCTION SET 3.1 Functional Summary No tat ion Assembly-Language Instructions 3-5 SECTION 4 STRUCTURING A Z8 PROGRAM 4.1 Introduction Program Structure Modules Procedures.. DO Loops.. IF Statements... Scope Summary Relocatabil i ty Sections..., Location Counter Control Modes of Arithmetic Expressions 4-10 SECTION 5 PLZ/ASM HIGH-LEVEL STATEMENTS 5.1 Z8 Source Program Statements Pr09ram Structuring Statements Module Declaration..... Procedure Declaration. DO Statement.. IF S tat em e n t.... IF-CASE Statement Jump Opt imi zation vi CONTENTS (cont.) SECTION 5 PLZ/ASM HIGH-LEVEL STATEMENTS (cont.) 5.3 Defining Data Constant Definition Data Types Type Definition Variable Declaration Label Declaration SIZEOF Operator APPENDIX A APPENDIX B APPENDIX C ASSEMBLY-LANGUAGE INSTRUCTION SUMMARY HIGH-LEVEL STATEMENT SUMMARY ASSEMBLER DIRECTIVES AND PSEUDO INSTRUCTIONS C.l Assembler Directives..... C-l C.2 Pseudo Instructions C-4 C.3 Conditional Assembly. C-4 APPENDIX D RESERVED WORDS AND SPECIAL CHARACTERS D.l Reserved Words... D-l D.2 Special Characters. D-2 APPENDIX E ASCII CHARACTER SET INDEX vi i LIST OF ILLUSTRATIONS Figure Z8 Memory Segments. Working-Reg ister Groups Control Reg isters.... Data Lengths.... Z8 Architecture Diagram Z8 Pin Functions and Assignments viii Section 1 Architectural Overview 1.1 Introduction Zilog's Z8 microcomputer introduces a new generation of single-chip architecture. Compared to earlier single-chip microcomputers, the Z8 offers faster execution, more efficient use of memory, more sophisticated interrupt, input/output (I/O), and bit-manipulation capabilities, and easier system expansion. Under program control, the Z8 configuration can be tailored to the needs of its user. It can serve as an I/O-intensive microcomputer, as an intelligent peripheral controller within a larger system, or as a memory-intensive microprocessor. The Z8's features include a powerful repertoire of 43 instructions, similar in form to the instruction sets of the Z80 and Z8000 microprocessor families. The efficiency of these instructions and of the Z8's internal register-addressing scheme not only speeds program execution, but also packs more program into the Z8 chip than would be possible with comparable microcomputers. This is, of course, extremely important for single-chip devices where on-chip memory space is limited. Real-time control applications, for which the Z8 is particularly suited, require fast instruction execution and fast interrupt response. Operating from an 8 MHz clock source (internal 4 MHz clock rate), the Z8 executes most instructions in 1.5 to 2.5 microseconds (6 to 10 machine cycles). The longest instruction takes 5 microseconds (20 cycles). The following summarizes the main features of the Z8: 40-pin package, offering more I/O program control than previously available in single-chip microcomputers; On-chip, 2K-byte, read-only (ROM) program memory with possible expansion by 62K of external program memory; On-chip, 144-byte, random-access (RAM) register memory, including 4 I/O ports and 16 control registers; Possible 62K bytes external data memory; Six maskable and prioritized interrupts; Two on-chip interval timers, also programmable as event counters; 1-1 Independent on-chip UART with hardware parity generator and checker; On-chip clock for internal timing. The remainder of this section describes in more detail those Z8 features of primary interest to assembly-language programmers. See the Z8 Technical Manual for detailed architectural and configuration information. 1.2 Memory Segments As shown in Figure 1-1, the 28 has three separate memory segments for storing program instructions and data. Program memory (chip resident or external) Data memory (external) Register memory (chip resident) The latter includes I/O registers, control and status registers, and general purpose data registers r , ,65535 EXTERNAL ROM OR RAM EXTERNAL RAM CONTROL AND STATUS REGISTERS NOT IMPLEMENTED r t~g:~ ~~!~ GENERAL REGISTERS ON CHIP ROM NOT ADDRESSABLE 110 PORT REGISTERS PROGRAM MEMORY DATA MEMORY REGISTER MEMORY (ON CHIP RAM) Figure 1-1. Z8 Memory Segments 1-2 The Z8 hardware environment must be specifically configured to access external program or data memory. Both segments can be accessed by 16-bit addresses Program Memory The first 2048 bytes of program memory consist of on-chip programmable storage addressed by the program counter. For addresses 2048 or greater, the Z8 automatically executes external program memory fetches (provided the Z8 is configured accordingly). The first example below jumps to address 1500 if the Zero flag (Z) is set. The second calls a procedure whose starting address is location in external program memory. JP Z,1500 CALL The first 12 bytes of program memory are reserved for the Z8's interrupt mechanism. Addresses 0-11 contain six l6-bit addresses corresponding to the six possible interrupts available on the Z8, IRQO through IRQ5, respectively. When an interrupt occurs, control passes to the address corresponding to that particular interrupt. A system reset forces the program counter to 12, the first address available for the user program. See the discussion of interrupts in Section External Data Memory A Z8 system can directly access as much as 62K bytes of external data memory. This segment is addressed beginning with data address External I/O is also mapped into this segment Register Memory Register memory includes 124 general-purpose registers, 4 I/O ports, and 16 status and control registers. The I/O port and control registers are-rncluded in register memory to allow any Z8 instruction to process I/O or control information directly, thus eliminating the need for special I/O or control instructions. The Z8 instruction set permits direct access to any of these 144 registers. Each of the 124 general-purpose registers can function as an accumulator, an address pointer, or an index register. 1-3 Z8 instructions can access registers directly or indirectly using an 8-bit address field. The Z8 also allows 4-bit addressing of registers, which generally saves bytes, and speeds program execution and task switching. In this 4-bit addressing mode, the register file is divided into 9 working-register groups, each occupying 16 contiguous register locations (Figure 1-2). A register pointer (one of the control registers) addresses the starting location of the currently active working-register group. (DEC) (HEX) F CONTROL REGISTERS, F UNUSED 128 r Figure 1-2. Working-Register Groups 1-4 NOTE: Changing the value of the register pointer is an easy way to save the 16 currently-active working registers (as during interrupt processing). Reserving one or more working-register groups for the use of interrupt-handling routines is a recommended programming practice. In the following example, the Set Register Pointer (SRP) instruction sets the register pointer to 240, the starting address of the control register group. The following Load (LD) instruction initializes register 252 to ten. SRP #240 LD R12, #10!Register Pointer contains FO (hex)!!working register 12 occupies register location 252! Because of their special significance, the I/O port registers (0-3) and control registers ( ) are referenced later in this section. The control registers are particularly pervasive in all Z8 operations, since they are used in the handling of I/O, interrupts, the timer/counter, program control flags, and the program stack, as well as to point to the current working-register group. To provide a quick reference in the following sections, the control registers are listed in Figure 1-3. They are described in bit-level detail in the Z8 Technical Manual. Z8 instructions can reference control registers by number or by their predefined symbolic identifiers shown in the following figure. NOTE Register memory addresses do not exist and should not be specified in Z8 instructions. The result of accessing these locations is undefined. 1-5 LOCATION STACK POINTER (BITS 7-0) STACK POINTER (BITS 15-8) REGISTER POINTER PROGRAM CONTROL FLAGS INTERRUPT MASK REGISTER INTERRUPT REOUEST REGISTER INTERRUPT PRIORITY REGISTER PORTS 0-1 MODE PORT 3 MODE PORT 2 MODE TO PRESCALER LOAD TIMER/COUNTER 0 LOAD T1 PRESCALER LOAD TIMER/COUNTER 1 LOAD TIMER MODE SERIAL I/O NOT IMPLEMENTED IDENTIFIERS SPL SPH RP FLAGS IMR IRO IPR P01M P3M P2M PREO TO PRE1 T1 TMR SIO 127 GENERAL PURPOSE REGISTERS PORT 3 PORT 2 PORT 1 PORTO P3 P2 P1 PO Figure 1-3. Control Registers 1-6 1.2.4 Data Lengths Z8 instructions can operate on individual bits, 4-bit Binary Coded Decimal (BCD) digits or nibbles, 8-bit bytes, or 16-bit words (Figure 1-4). Bits can be set, reset, or tested. Nibbles are used in BCD arithmetic operations. Bytes are used for character or small integer values (in the range 0 to 255 if unsigned, or in the range -128 to 127 if signed). Words are used for larger integer values (in the range 0 to if unsigned, or in the range to if signed). The basic data element of the Z8 is the byte. Memory locations (whether they reside in program, data, or register memory segments) are ordinarily accessed eight bits at a time. Increment Word (INCW) and Decrement Word (DECW) are the only instructions that operate on 16-bit words I I I I I I I I BITS IN A BYTE UPPER LOWER NIBBLES IN A BYTE!, I I I! BYTE UPPER BYTE,,! LOWER BYTE,,, WORD! I Figure 1-4. Data Lengths 1-7 1.3 Input/Output Thirty-two of the 28's 40 lines are dedicated to input and output. These 32 lines are grouped into 4 ports of 8 lines each and can be configured as input, output, or address/data. Under software control, the ports can be programmed to provide timing, interrupt requests, status signals, and serial or parallel I/O features with or without handshake. In the following explanation of the various port functions, Port 1 is described before Port 0 for convenience. The 28 architecture diagrams (Figures 1-5 and 1-6) show the I/O lines and signals referenced. Although they are pictured separately in Figure 1-5, remember that from a programming standpoint the I/O ports, timers, interrupt controls, flags, and register pointer are all manipulated through register memory Port 1 Port 1 can be programmed as a byte I/O port or as an address/data port for interfacing to external memory. Associated with Port 1 are the Address Strobe (AS), Data Strobe (OS) and Read/Write (R/W) timing signals. Under program control, two lines from Port 3 (lines P33 and P34) can be used with Port 1 as the handshake control lines (OAVI and ROYl) or as a Port 1 interrupt request input (IRQl) and an external data memory access (OM) status output. If external data memory is to be accessed, Port 1 is programmed as an address/data port through which the external address and data are passed. In this case, the lower eight bits of the address (AO-A7) are multiplexed with data bits (00-07). If an address longer than eight bits is required, the additional address bits (A8-A15) originate from Port O Port 0 Port 0 can be programmed to be either an I/O port or an address output for external memory. Depending on the size of the address, Port 0 provides either bits 8-11 or bits 8-15 of the address. (Port 1 provides bits 0-7). If the address is 12 bits or less, the upper four bits (nibble) of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. When Port 0 is used in the I/O mode, two lines from Port 3 (lines P32 and P35) can be used for the handshake controls DAVO and ROYO. 1-8 OUTPUT INPUT XTAL AS DS R/W RESET UO ADDRESS OR 1/0 ADDRESSIDATA OR 1/0 (BIT PROGRAMMABLE) (NIBBLE PROGRAMMABLE) (BYTE PROGRAMMABLE) Figure 1-5. Z8 Architecture Diagram RESET +5V +5V P3, R/W GND AND XTAL2 P3, n ' 1 - CONTROL os XTALl '-}CLOCK XTAL1 P2, AS XTAL2 P3, P2, POo P20.- P30 P2, PO, P2, RESET - P PO, P2,.- PORTO PORT 2 R/W P2, (NIBBLE...- PO, P2, (BIT PRO DS P2, PROGRAMMABLE)...- PO P2. GRAMMABLE) 110 OR AD8-AD AS P2,...- PO, P2, ---- ZB P35 P20 PO, MCU P2, GND P3, PO, P2, P3, P3. Pl P30 P3, POo Pl, Pl, PO, Pl, Pl, P3, PORT 3 PORT 1 PO, P1 5 P3, -- (FOUR INPUT; (BYTE Pl, FOUR OUTPUT). PO, Pl. PROGRAMMABLE) - Pl. P3. SERIAL AND 1/0 OR ADo-AD7 PARALLEL 110 PO. Pl, P1 5 P35 AND CONTROL Pl, P3, P05 Pl, --- Pl, P3, -- PO, Pl,...- PO, Pl0 Figure 1-6. Z8 Pin Functions and Assignments 1-9 1.3.3 Port 2 Port 2 can be programmed for input or output on a line-by-line (bitwise) basis. As in the case of Ports 0 and 1, two lines from Port 3 (lines P31 and P36) can be programmed as the handshake control lines DAV2 and RDY2. The output buffers of Port 2 have a programmable option for inhibiting the active pull-ups to provide open-drain type outputs Port 3 Port 3 can be programmed for I/O and/or as a control port. In I/O mode, the direction of the eight lines is fixed as four in and four out. The control functions of Port 3 are handshake, interrupt request, timer in and out, and status out. Two lines of Port 3 can be programmed as a serial input and a serial output interface. Each line has an 8-bit serial/ parallel register associated with it. Serial I/O uses an asynchronous format with the bit rate controlled by the internal timer. Interrupts are generated when a character is received or transmi tted. 1.4 Interrupts rhe Z8 allows six different interrupts from eight possible,ources -- the four input lines of Port 3, serial in and out, and :he two timers (TO and Tl, discussed in Section 1.5). 3ix bits in the Interrupt-Mask control register can enable/ lisable the six interrupts IRQO-IRQ5 individually. When more :han one interrupt is pending, priorities are resolved by a )riority encoder, controlled by the Interrupt-Priority control :egister. ~terrupt requests are stored in an Interrupt-Request control egister, which can also be used for polling. When an interrupt equest is granted, the Z8 enters an interrupt machine cycle :hat globally disables all other interrupts, saves the program :ounter (address of the next program instruction to be executed) lnd status flags, and finally branches to the vector location for ~e interrupt. It is only at this point that control passes to.he interrupt-handling procedure for the interrupt. lefore the Z8 can recognize interrupts following RESET, some nitialization tasks must be performed. RESET causes the nterrupt Request Register (IRQO - IRQ5) to be cleared and held o zero, and interrupts to be globally disabled (bit 7 of the nterrupt Mask Register = 0). The initialization routine should onfigure the Z8 interrupt requests to be enabled/disabled (via 1-10 the IMR) as required by the target application, and prioritized for vectored interrupts (via the Interrupt Priority Register). Because RESET holds the IRQ register to zero, one final step is required before interrupts can function, even in polled mode. Specifically, interrupts must be globally enabled via the EI instruction; simply setting bit 7 of IMR is not sufficient. Subsequent to this EI, interrupts can be enabled either by IMR register manipulation or by use of the EI instruction, with equivalent effects. Additionally interrupts must be disabled by executing a DI instruction before the IPR or IMR control registers can be modified. Interrupts can then be enabled by executing an EI instruction. 1.5 Timers/Counters The Z8 has two 8-bit counters (TO and Tl), each driven by its own 6-bit prescaler. The prescalers can be driven, in turn, by either an internal (TO and Tl) or external (Tl only) clock source. TO and Tl can operate independently of the processor instruction sequence and, consequently, can unburden the program from time-critical operations like event counting or elapsed-time calculation. Each prescaler can be programmed to divide the input frequency of its clock source by any number from 1 to 64. The prescaler drives its counter, which decrements a value (0 through 255) stored in the timer register. When the timer register reaches end-of-count, a timer interrupt request--irq4 (TO) or IRQ5 (Tl)--is generated. Under program control, counters/prescalers can be started, stopped, restarted to continue counting, or restarted from the initial value of the counters. The counters can also be programmed to stop on reaching end-of-count, or to automatically reload the initial counter value and continue counting. Elther counter can be read at any time without disturbing its value or count mode. The clock source for the Tl counter/prescaler can be either the microprocessor clock or an external timer input. Under program control, the external timer input can function as an external clock (maximum frequency 1 MHz), a trigger input that can be retriggerable or not, or as a gate input for the internal clock. 1-11 )ne line of Port 3 also serves as a timer output through which ro, Tl, or the internal clock can be output. The timer output :oggles whenever an end-of-count occurs. If the timer is )rogrammed to reload the count value and continue at!nd-of-count, this line produces a 50% duty cycle. The counters :an be cascaded by feeding the timer input line with the timer )utput. l.6 Status Flags and Program Controls rhe ability to test data and make decisions based on the result s especially important in single-chip microcomputers. Programs lritten for these computers tend to be dominated by control nstructions (conditional and unco
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