Specification BT46121 BTHQ128064AVC1-STF-06-LED02YG-COG_BT PDF

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Specification BT46121 BTHQ128064AVC1-STF-06-LED02YG-COG_BT46121 Version: Dezember 2015 DOCUMENT REVISION HISTORY DOCUMENT REVISION DATE FROM TO A First Release. DESCRIPTION Based on a.) Test
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Specification BT46121 BTHQ128064AVC1-STF-06-LED02YG-COG_BT46121 Version: Dezember 2015 DOCUMENT REVISION HISTORY DOCUMENT REVISION DATE FROM TO A First Release. DESCRIPTION Based on a.) Test Specification: VL-TS-COG-BTC12864-XX REV.E, b.) VL-QUA-012B REV.W According to VL-QUA-012B, LCD size is small because Unit Per Laminate=15 which is more than 6pcs/Laminate. CHANGED BY LINDA ZHU CHECKED BY LIN RONG SHOU A B Items 1 to 11 were updated: 1.) (Whole document) The numbers of whole pages & points were updated. 2.) (Page 4, Table 1) Weight was added. 3.) (Page 10, Table 5) Notes were updated. 4.) (Page 15, Point 5.3) Initial Code Setting was added. 5.) (Page 16, Point 5.4) Power Up Sequence was added. 6.) (Page 17, Point 5.5) Power Down Sequence was added. 7.) (Page 18~19, Point 6) Electro-Optical Characteristics was added 8.) (Page 20, Point 7) Reliability Conditions was added. 9.) (Page 21~34, Point 8) LCD Cosmetic Conditions was updated. 10.) (Page 35~36, Point 9) Packing Removal and Handling Requirement was added. 11.) (Page 37, Point 10) Remark was updated. LI TING JIN YOU PING CONTENTS Page No. 1. GENERAL DESCRIPTION 4 2. MECHANICAL SPECIFICATIONS 4 3. INTERFACE SIGNALS 8 4. ABSOLUTE MAXIMUM RATINGS ELECTRICAL MAXIMUM RATINGS - FOR IC ONLY ENVIRONMENTAL CONDITION 9 5. ELECTRICAL SPECIFICATIONS TYPICAL ELECTRICAL CHARACTERISTICS TIMING SPECIFICATIONS INITIAL CODE SETTING (FOR REFERENCE ONLY) POWER UP SEQUENCE POWER DOWN SEQUENCE ELECTRO-OPTICAL CHARACTERISTICS OPTICAL CHARACTERISTICS DEFINITION RELIABILITY CONDITIONS LCD COSMETIC CONDITIONS PACKING REMOVAL AND HANDLING REQUIREMENT REMARK 37 Specification of LCD Module Type Item No.: COG-BTC General Description 128 x 64 dots STN Yellow Positive Transflective LCD Graphic Module. Viewing Angle: 6 O clock. Driving scheme: 1/65 duty, 1/9 bias. ULTRACHIP UC1601 (COG) LCD Controller-Driver or equivalent. Logic voltage: +3V. FPC connection. Yellow Green LED02 Backlight. RoHS compliance. 2. Mechanical Specifications The mechanical detail is shown in Fig. 1 and summarized in Table 1 below. Table 1 Parameter Specifications Unit Outline dimensions 67.5(W) x 82.5(H) x 8.5(D)(Include FPC and Backlight) mm Viewing area MIN.(W) x MIN.(H) mm Active area (W) x (H) mm Display format 128 x 64 dots Dot size 0.43(W) x 0.57(H) mm Dot spacing 0.015(W) x 0.015(H) mm Dot pitch 0.445(W) x 0.585(H) mm Weight: Approx: 25 grams VLCD VB0+ VB0- VB1- PS1 PS0 VB1+ VSS VDD D0(SCK),D1, D2,D3(SDA)~D7 RD WR CD RST CS0 8 DOT MATRIX LCD CONTROLLER- DRIVER 'ULTRACHIP' UC1601 (COG) OR EQUIVALENT 64 COG-BTC12864 LCD GRAPHIC DISPLAY 128 X 64 DOTS 128 K2 A2 K1 A1 YELLOW GREEN LED02 BACKLIGHT Figure 2: Block diagram 3. Interface Signals Table 2 Pin No. Symbol Description 1 CS0 2 RST 3 CD 4 WR 5 RD 6 D0(SCK) 7 D1 8 D2 9 D3(SDA) 10 D4 11 D5 12 D6 13 D7 14 VDD Chip Select. In parallel mode and S8 mode, chip is selected when CS0 = L and CS1= H. When the chip is not selected, D [7:0] may be high impedance. When RST = L, all control registers are re-initialized by their default states. When RST is not used, connect the pin to VDD. Select Command or Display Data for read/write operation. L : Command H : Display data RD /WR 15 VSS Ground. 17 PS0 18 PS1 16 VB1+ 19 VB1-20 VB0-21 VB0+ (WR [1:0]) controls the read/write operation of the host interface. /WR In parallel mode, RD (WR [1:0]) meaning depends on whether the interface is in the 6800 mode or the 8080 mode. In serial interface modes, these two pins are not used. Connect to VSS. Bi-directional bus for both serial and parallel host interfaces. In S8 and S9 mode, connect unused pins to VDD or VSS. PS=1x Ps=0x D0 D0 SCK D1 D1 D2 D2 D3 D3 SDA D4 D4 D5 D5 D6 D6 D7 D7 VDD1 is the digital power supply and it should be connected to a voltage source that is no higher than VDD2&3. VDD2&3 is the analog power supply and it should be connected to the same power source. Minimize the trace resistance for VDD2&3. PS [1:0] Parallel/Serial. Serial modes: LL : serial (S8) LH : serial (S9) Parallel modes: HL : 8080 HH : 6800 LCD Bias Voltages. These are the voltage sources to provide SEG driving currents. These voltages are generated internally. Connect capacitors of CBX value between VBX+ and VBX. The resistance of these four traces directly affects the SEG driving strength of the resulting LCD module. Minimize the trace resistance is critical in achieving high quality image. 22 VLCD Main LCD Power Supply. A by-pass capacitor CL is optional. When CL is used, connect CL between VLCD and VSS, and keep the trace resistance under 300 Ohm. - A Anode of LED Backlight. - K Cathode of LED Backlight. 4. Absolute Maximum Ratings 4.1 Electrical Maximum Ratings for IC Only Table 3 Parameter Symbol Min. Max. Unit Logic supply voltage V DD V LCD generator supply voltage V DD V Analog circuit supply voltage V DD V Voltage difference between V DD and V DD2/3 V DD2/3 - V DD V LCD generated voltage V LCD V Any input/output V IN/ / V OUT -0.4 V DD +0.3 V Note: 1. V DD is based on V SS = 0V. 2. Stress values listed above may cause permanent damages to the device. 4.2 Environmental Condition Item Table 4 Operating Temperature (Topr) Storage Temperature (Tstg) (Note 1) Min. Max. Min. Max. Ambient Temperature 0 C +50 C -10 C +60 C Dry 90% max. RH for Ta 40 C Humidity (Note 1) 50% RH for 40 C Ta Maximum operating temperature Vibration (IEC ) cells must be mounted on a suitable connector Shock (IEC ) Half-sine pulse shape Frequency: Hz Amplitude: 0.75 mm Duration: 20 cycles in each direction. Pulse duration: 11 ms Peak acceleration: 981 m/s 2 = 100g Number of shocks: 3 shocks in 3 mutually perpendicular axes. Note 1: Product cannot sustain at extreme storage conditions for long time. Remark No condensation 3 directions 3 directions 5. Electrical Specifications 5.1 Typical Electrical Characteristics At Ta = 25 C, VDD = 3V±5%, VSS=0V. Table 5 Parameter Symbol Conditions Min. Typ. Max. Unit Supply voltage (Logic VDD-VSS & booster) V LCD driving voltage VLCD-VSS Ta = 0 C, (Built-in) VDD = 3V, Note V At Ta = +25 C, VDD = 3V, Note V At Ta = +50 C, VDD = 3V, Note V Input signal voltage V IH H level 0.8 VDD1 - - V V IL L level VDD1 V Supply Current IDD Character mode, (Logic & booster) VDD = 3V, Note ma Checker board mode, VDD = 3V, Note ma Supply Voltage of VLED Forward current Yellow Green LED02 =120mA V backlight Wavelength of Yellow λ Green LED02 backlight Number of LED nm Luminance (on the chips =2x4=8 dies. cd/m backlight surface) Note 1: There is tolerance in optimum LCD driving voltage during production. Minimum and maximum LCD driving voltages indicate the range of optimum LCD driving voltage shift due to production tolerance. Please adjust LCD driving voltage manually to obtain the best module performance. Note 2: Do not display a fixed pattern for more than 30 min. because it may cause image sticking due to LCD characteristics. It is recommended to change display pattern frequently. If customer must fix display pattern on the screen, please consider to activate screen saver. Note 3: Backlight ambient temperature vs. suggested derating curve of forward current: 5.2 Timing Specifications Parallel bus timing characteristics (for 8080 MCU) At Ta= 0 C to +50 C,VDD=3V±5%, VSS=0V. Figure 4: Parallel Bus Timing Characteristics (for 8080 MCU) At Ta= 0 C to +50 C,VDD=3V±5%, VSS=0V. Parallel bus timing characteristics (for 6800 MCU) At Ta= 0 C to +50 C,VDD=3V±5%, VSS=0V. Figure 5: Parallel Bus Timing Characteristics (for 6800 MCU) At Ta= 0 C to +50 C,VDD=3V±5%, VSS=0V. Serial Bus Timing Characteristics (for S8) At Ta= 0 C to +50 C,VDD=3V±5%, VSS=0V. Figure 6: Serial Bus Timing Characteristics (for S8) At Ta= 0 C to +50 C,VDD=3V±5%, VSS=0V. Serial bus timing characteristics (for S9) At Ta= 0 C to +50 C,VDD=3V±5%, VSS=0V. Figure 7: Serial Bus Timing Characteristics (for S9) At Ta= 0 C to +50 C,VDD=3V±5%, VSS=0V. Reset characteristics At Ta= 0 C to +50 C,VDD=3V±5%, VSS=0V. Figure 8: Reset Characteristics At Ta= 0 C to +50 C,VDD=3V±5%, VSS=0V. 5.3 Initial Code Setting (for reference only) Table 6 Command Reset LCD bias set Multiplexing rate set Set LCD loading Temp. Compensation Set RAM address control Set LCD Mapping Control Set frame rate Electronic volume mode set Electronic volume Power control set Display start line set Page address set Column address upper bit set Column address lower bit set Display normal or reverse Display enable Setting 0XE2 0XEB 0X23 0X29 0X24 0X89 0XC6 0XA0 0X81 0X5A 0X2F 0X40 0XB0 0X10 0X00 0XA6 0XAF 5.4 Power Up Sequence UC1601 power-up sequence is simplified by built-in Power Ready flags and by the automatic invocation of System-Reset command after Power-ON-Reset. System programmer is required to wait for only 5~10mS before starting to issue commands to UC1601. No additional commands or waits are required between enabling of the charge pump, turning on the display drivers, writing to RAM or any other commands. However, while turning on VDD, Vdd2/3 should be started not later than VDD. Delay allowance between VDD and VDD2/3 is illustrated as Figure 11. 5.5 Power Down Sequence To prevent the charge stored in capacitor CL from causing abnormal residue horizontal line on display when VDD is switched off, use Reset mode to enable the built-in charge draining circuit to discharge these external capacitors. UC1601 will not drain VLCD when internal VLCD is not used. System designer should take care to make sure external VLCD source is properly drained off before turning off VDD. Figure 10: Reference Power-Down Sequence Figure 11: Delay allowance and Power Off-On Sequence 6. Electro-Optical Characteristics Item Symbol Table 7 Temp. Value C Min. Typ. Max. Unit Driving voltage Vop (VLCD-VSS) Response time Ton Toff msec θ1(6 o clock) 40 50 - Optimum θ2(12 o clock) 40 50 - viewing area +25 φ1(3 o clock) Cr 2 φ2(9 o clock) DEG Contrast ratio Cr Transmittance T (n_sel) % Condition Vop= optimum voltage (Remark 1) Vop= Optimum voltage θ = 0, φ = 0 φ = 0 θ = 0 Vop= Optimum voltage (Remark 2) Vop = Optimum voltage θ = 0, φ = 0 Remark 1: There is tolerance in optimum LCD driving voltage during production. Minimum and maximum LCD driving voltages indicate the range of optimum LCD driving voltage shift due to production tolerance. Please adjust LCD driving voltage manually to obtain the best module performance. Remark 2: Due to hardware limitation, the maximum measurable angle is 50 C. Remark 3: All the EOC data are measured by DMS505 (DMS2#). Remark 4: All the EOC data are measured with Y-G backlight (Module). ISO plat at 25 C 6.1 Optical Characteristics Definition a.) Viewing Angle b.) Contrast Ratio B1 = segments luminance in case of non-selected waveform B2 = segments luminance in case of selected waveform Non-selected dot Contrast Ratio is defined by Cr = B2/B1 Selected dot Luminance 100% B2 B1 Select waveform Non-select waveform Vop c.) Response Time Non-selecected condition Selected Condition Non-selecected condition 90 % 10 % 100 % Luminance Ton rise time Toff fall time 7. Reliability Conditions Table 8 Test items Test Condition Sample Qty. Temperature shock storage -10 C/1hrs To +60 C/1hrs, Total 32cycles 10PCS Low temperature operating 0 C operating 240hrs 10PCS High temperature operating +50 C operating 240hrs 10PCS HTHH operating 40 C, 93%RH, operating 240hrs 10PCS Temperature cycling 0 C/1hr To +50 C/1hr 2.5hrs per cycle operating Total 60 cycles. Operating 10PCS Vibration test D=1.5mm;F=10~50Hz; 20 cycles, 2hrs;X/Y/Z directions 10PCS ESD Test 150pF,330 Ohm; Air :±10KV,10mm distance; contact: ±6KV. Only for display area, if display can resume after program was reset, it s OK 5+5PCS Low temperature storage -10 C storage 240hour 10PCS 8. LCD Cosmetic Conditions a.) Reference document for following VL-QUA-012B. b.) LCD size of the product is small. 9. Packing Removal and Handling Requirement Headquarters: DATA MODUL AG Landsberger Str. 322 DE Munich - Germany Phone: Fax: Logistics, Production & Services: DATA MODUL Weikersheim GmbH Lindenstrasse 8 DE Weikersheim - Germany Phone: Fax: Subsidiaries & Sales Offices: Germany Hamburg Germany Duesseldorf Denmark Dubai Finland/Baltic France Italy Singapore Spain Switzerland UK USA DATA MODUL s worldwide offices can be found on our website: contact-us/offices.html Data Modul
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