IMPORTANT NOTICE. Company name - STMicroelectronics NV is replaced with ST-NXP Wireless. - PDF

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IMPORTANT NOTICE Dear customer, As from August 2 nd 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to
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IMPORTANT NOTICE Dear customer, As from August 2 nd 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document. Company name - STMicroelectronics NV is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of the last page STMicroelectronics 200x - All rights reserved, shall now read: ST-NXP Wireless 200x - All rights reserved. Web site - is replaced with Contact information - the list of sales offices is found at under Contacts. If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless Mobile multimedia application processor Nomadik is a registered trademark of STMicroelectronics Data Brief Features Smart video accelerator MPEG-4 SP real-time encoding/decoding up to SDTV 30 fps H.264/AVC real-time decoding up to VGA 30 fps and encoding up to VGA 15 fps WM9/VC-1 encode/decode support JPEG encode up to 30 Mpixel/s, decode up to 15 Mpixel/s Smart audio accelerator with extensive digitalaudio software library Smart imaging accelerator 5 Mpixel camera support 2 SMIA CCP2 camera interfaces up to 650 Mbit/s and parallel camera CCIR-656 interface up to 80 MHz Real-time image reconstruction up to 80 Mpixel/s and 10-bit raw Bayer interface Smart graphics accelerator Ultra low-power implementation TV output Advanced power management unit ARM926EJ 32-bit RISC CPU, up to 393 MHz 16-Kbyte instruction cache, 16-Kbyte data cache, 128-Kbyte level 2 cache On-chip SRAM: 512 Kbytes + 16 Kbytes with secured access + 1 Kbyte backup On-chip ROM: 32 Kbytes for boot + 64 Kbytes with secured access Enhanced security framework and protected access to secured ROM and RAM 16-bit DDR/SDR-SDRAM memory controller (up to 166 MHz) NOR Flash/NAND Flash/CompactFlash/CF+ controller VFBGA 14.0mm x 14.0mm x 1.0mm memory stackable package (PoP) Description The STn8815 application processor enables smart phones, mobile multimedia, internet appliances and in-car entertainment systems to playback media content, record video clips and pictures, receive mobile-tv and perform real-time bidirectional audio-visual communication. Figure 1. STn8815P14 block diagram Memory top package DDR interface NAND/NOR Flash controller DDR SDRAM controller Smart imaging accelerator Color LCD controller Display interfaces Camera interfaces x2 Host port interface Multichannel DMA controller Secured RAM/ROM esram buffer Smart video accelerator Smart audio accelerator Camera interfaces x2 USB-OTG HS x2 I²C x2 HSI MSP x4 SD/MMC Timers Watchdog RTC System controller Interrupt controller Power management Security toolbox PLLs Dcache Icache ARM926EJ JTAG/trace UART x3 SSP FIrDA 1-Wire/HDQ interface GPIO x 124 January 2008 Rev 1 1/22 For further information contact your local STMicroelectronics sales office. 22 Contents STn8815P14 Contents 1 STn8815P14 overview Key benefits Main features Low power consumption Open platform strategy Memory package interfaces Architecture overview Smart video accelerator (SVA) Smart audio accelerator (SAA) Smart imaging accelerator (SIA) Smart graphics accelerator (SGA) Advanced power management unit (PMU) ARM926EJ processor Embedded memory units Advanced security Flexible static memory controller (FSMC) SDRAM memory controller (SDMC) Real time clock (RTC) Timers Watchdog timer Vectored interrupt controller (VIC) System and reset controller (SRC) Direct memory access (DMA) controllers Universal asynchronous receivers-transmitters (UARTs) Synchronous serial port (SSP) Camera interfaces TV interface Liquid crystal display controller (LCDC) Master display interface (MDIF) Pulse width light modulator (PWL) /22 Contents 2.24 General purpose inputs/outputs (GPIOs) Memory card interface (MMC/SD/MS) USB-OTG high-speed interface I 2 C bus interface Fast IrDA interface (FIrDA) Multichannel serial ports (MSP) Scroll key and keypad encoder (SKE) interface High-speed serial interface (HSI) Host port interface (HPI) Package mechanical data Ordering information Revision history /22 overview STn8815P14 1 STn8815P14 overview Smart video accelerator MPEG-4 SP real-time encoding/decoding up to SDTV 30 fps H.264/AVC real-time decoding up to VGA 30 fps and encoding up to VGA 15 fps WM9/VC-1 encode/decode support JPEG encode up to 30 Mpixel/s, decode up to 15 Mpixel/s Ultra low-power implementation Smart audio accelerator Extensive digital-audio software library Ultra low-power implementation Smart imaging accelerator 5 Mpixel camera support 2 SMIA CCP2 camera interfaces up to 650 Mbit/s Parallel camera CCIR-656 interface up to 80 MHz Real-time image reconstruction up to 80 Mpixel/s 10-bit raw Bayer interface Ultra low-power implementation Smart graphics accelerator for 2-D and 3-D OSD TV output Advanced power management unit Run, idle, doze and sleep modes CPU clock with programmable frequency Enhanced dynamic power-domain management Dynamic voltage scaling ARM926EJ 32-bit RISC CPU, up to 393 MHz 16-Kbyte instruction cache, 16-Kbyte data cache 128-Kbyte level 2 cache 3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code density, byte Java mode (Jazelle ) for direct execution of Java code Embedded medium trace module (ETM Medium+) On-chip SRAM: 512 Kbytes + 16 Kbytes with secured access + 1 Kbyte backup On-chip ROM: 32 Kbytes for boot + 64 Kbytes with secured access Advanced security Enhanced security framework Protected access to secured ROM and RAM 16-bit DDR/SDR-SDRAM memory controller (up to 166 MHz) NOR Flash/NAND Flash/CompactFlash/CF+ controller High-speed MMC/SD Card/Memory Stick Pro host controller 4/22 STn8815P14 overview Color LCD controller for STN or TFT panels or display interface for display module 24-bpp true color MIPI legacy DBI and DPI Two high speed USB 2.0 On-The-Go controller interfaces (12 and 480 Mbit/s) ULPI v1.1 compliance ULPI SDR support, DDR not supported Host port interface I/O peripherals 3 autobaud UARTs (one with modem control signals) up to 6 Mbit/s One IrDA (SIR/MIR/FIR) interface up to 4 Mbit/s One synchronous serial port (SSP) up to 24 Mbit/s 4 multichannel serial ports (MSP) up to 48 Mbit/s 3 I²C master/slave interfaces, 1 dedicated to SIA Two 8-channel, full-duplex high-speed serial interfaces, 110 Mbit/s (MIPI legacy HSI) Rotary encoder interface; keypad matrix interface 1-Wire /HDQ interface (a) 124 general-purpose I/Os (muxed with peripheral I/Os) System and peripheral controller Multichannel DMA controller 64-source interrupt controller Eight 32-bit timers/counters Real-time clock (RTC) Real-time timer (RTT) Watchdog timer Programmable PLL for CPU and system clocks Two crystal oscillators: 32 khz and 13/19.2 MHz JTAG IEEE boundary scan Supply voltages 1.2 V to 1.4 V logic; 1.8 V to 2.5 V I/O, PLL analog; 2.5 V OTP VFBGA memory stackable (package on package) 14 mm x 14 mm x 1.0 mm, pitch 0.5 mm, 464 balls a. 1-Wire is a registered trademark of Dallas Semiconductor. 5/22 overview STn8815P14 The convergence of computing, multimedia and mobile communications is well underway. Already the familiar voice phone is being transformed into a personal device with a wide range of multimedia capabilities. Soon mobile users will be able to benefit from a broad spectrum of multimedia features and services, to include capturing, sending and receiving images, videos and music. To deliver such data-heavy, processing-intensive services, portable handheld systems must be optimized for high performance but low power, space and cost. In response to this need, the STn8815P14 processor platform from STMicroelectronics is a culmination of breakthroughs in video coding efficiency, inventive algorithms and chip implementation schemes. It will enable smart phones, wireless PDAs, internet appliances and car entertainment systems to play back media content, record pictures and video clips, and perform bidirectional audio-visual communication with other systems in real time. The STn8815P14 focuses on the essential features to meet the future needs of mobile products and services: a high-performance multimedia capability coupled with low power consumption, and based on an open platform strategy. Figure 2. Typical system architecture using the STn8815P14 NAND Flash NOR Flash SRAM ROM CompactFlash/CF+ ATA device Rotary wheel Touch screen controller Keypad FSMC SKE LCD backlight SSP TFT Mono/color STN smart panel PWL CLCD/ MDIF Denc STw8009 TV output Camera1 Camera interfaces High-speed serial interface Host port interface Camera 2 I²C FIrDA Camera 3 RF GSM/GPRS/EDGE xcdma modem chip set Energy management STw4810 Fast IrDA Low-power SDRAM Mobile DDR SDRAM MMC SD-Card Memory Stick Pro SDMC MMCI ETM9 JTAG Nomadik STn8815 RTC Clock, reset UART I²C UART USB-OTG high speed MSP MSP I²S Bluetooth FM radio GPS module USB device x WLAN Digital TV demodulator Debug, trace Reset 32 khz 13/19.2 MHz Audio codecs STw5095 6/22 STn8815P14 overview 1.1 Key benefits The STn8815P14 brings the following key benefits to mobile manufacturers and consumers: Unsurpassed audio, video and imaging quality, Ultra-low power consumption for longer battery operation, Easier application development for shorter time-to-market, Scalability for multiple market segments and future multimedia applications. 1.2 Main features The STn8815P14 processor platform enables compelling multimedia applications by means of its unique distributed-processing architecture. The application processor features low-power smart accelerators which handle all audio, video and graphics functions. These free the main CPU for control and program flow tasks, or allow the CPU to enter power-saving modes to prolong battery life. The smart accelerators operate independently and concurrently to ensure the lowest absolute system power and deterministic high-performance. The main features of the platform are: A smart video accelerator for SDTV video encoding and decoding, with MIPI and SMIA camera interfaces. A smart audio accelerator containing a comprehensive set of digital audio decoders and encoders, and offering a large number of 3-D surround effects. A smart imaging accelerator, providing real-time, programmable image reconstruction engine. A smart graphics accelerator. A dynamic, multi-mode power management unit. The ARM926EJ processor, a powerful industry-standard CPU with Java acceleration. On-chip ROM and SRAM memory devices, including a 3-Mbit frame buffer. Security framework for enhanced mobile security, including stronger DRM. Multichannel DMA controller for efficient data transfer without CPU intervention. A multi-layer AMBA crossbar interconnect for optimized data transfers between the CPU, accelerators, memory devices and peripherals. Hardware semaphores for flexible inter-process management. A wide range of peripheral interfaces (GPIO, USB-OTG high speed, UART, I²C, FIrDA, SD/high-speed MMC/Memory Stick Pro, fast serial ports, TV output, color LCD and camera interfaces, scroll-key encoder, key-pad scanner). Direct support for high-level operating system such as Symbian, Linux and WinCE operating systems (OSs). 7/22 overview STn8815P Low power consumption The new multimedia functionality of mobile products brings with it an increase in power consumption that is outpacing advances in battery technology. The STn8815P14 chip saves on power by avoiding the need for high clock speeds wherever possible, but its extremely low power consumption results from a systematic effort at all design levels to reduce power requirements. These include: The use of smart accelerators and distributed processing to off load from the CPU, Efficient code execution by means of innovative algorithms, energy-efficient instruction set architectures and Java acceleration, The efficient use of bandwidth for on-chip data transport, achieved by data compression, buffering and image scaling, Aggressive power management which includes turning off inactive parts of the chip and keeping the CPU in power-saving modes as much as possible. 1.4 Open platform strategy STMicroelectronics is a founding member of the MIPI Alliance working towards mobile software and hardware interface standards. Our open platform strategy provides manufacturers with roadmap flexibility, allowing them to avoid becoming locked into a proprietary CPU architecture or vendor technology. This approach is facilitated by the following design points. The STn8815P14 employs the third-party ARM processor which is the standard CPU for mobile devices, with industry-wide application support. Open, standard APIs are provided for the development of application code on a level which is abstracted from the physical hardware. This allows the development of multimedia plug-ins that are portable between products and which can be reused on future products without modification. The STn8815P14 facilitates best-in-class algorithm development on its smart accelerators. The STn8815P14 is provided with development kits and tools that speed-up the integration of new operating systems, middleware, and signal processing algorithms. 1.5 Memory package interfaces The STN8815P14 package supports package on package technology, allowing a memory package to be stacked on top of the bottom package. The bottom package includes the STn8815P14 specific balls. Top lands of the STN8815P14 provide the following interfaces: mobile DDR SDRAM (16 bits data bus) OneNAND Some additional top lands can provide a complete mobile SDR/DDR interface connected directly to the bottom balls of the package, allowing an external processor to use memory from the top package. 8/22 Architecture overview 2 Architecture overview The STn8815P14 platform comprises an industry-standard ARM CPU supported by smart audio, video, imaging and graphics accelerators, on-chip memory and controllers, a rich set of peripheral interfaces, and a power management system. The processors, controllers, memory and peripheral interfaces are connected by a multi-layer advanced microcontroller bus architecture (AMBA) for efficient data transport between the components. The overall STn8815P14 architecture is illustrated in Figure 3. The main hardware components of the STn8815P14 are listed and outlined in the sections below. Figure 3. STn8815P14 block diagram LCD panel (STN/TFT/module) 3 cameras (parallel or TV serial) output Trace JTAG NOR NAND Flash control Backup RAM 1 KB Boot ROM 32 Kbytes LCD controller MDIF controller Smart imaging accelerator ETM/JTAG I/D cache 16/16 Kbytes L2 cache 128 Kbytes erom 64 Kbytes secured eram 16 Kbytes DDRcontrol SDRAM memory esram 512 Kbytes Smart video accelerator ARM926EJ secured Security toolbox Interconnect (data/instruction, memory/peripherals) Host port interface Vector interrupt controller Smart audio accelerator USB-OTG high speed (x2) HSI (x2) 124 GPIOs System control MSP (x4) interface 32 khz RTC PWL Timers (x8) Watchdog Smart graphics accelerator UART (x3) SD/MMC MS Pro interface Power manager RTT Secure watchdog Semaphores (x16) 13/19.2 MHz Clocks PLL CPU/buses/peripherals SSP I²C interface (x3) FIrDA interface Rotary encoder/ keypad interface 9/22 Architecture overview STn8815P Smart video accelerator (SVA) Using leading-edge technology, this block is a low-power, high-performance video accelerator that supports the following features: MPEG-4 simple profile level 5 video encoder and decoder; real-time up to SDTV 30 fps (encode only or decode only). MPEG-4 simple profile level 3 video simultaneous codec up to CIF 30 fps. H.264/AVC baseline profile level 3 decoding up to VGA 30 fps. H.264/AVC baseline profile level 2.2 encoding up to VGA 15 fps. H.264/AVC baseline profile level 2 simultaneous codec up to CIF 30 fps. WM9/VC-1 encode/decode support. JPEG baseline encoder acceleration up to 30 Mpixel/s. JPEG baseline and extended DCT-based decoder acceleration up to 15 Mpixel/s. Programmable DSP (MMDSP+) for intermediate level processing, clocked at up to 166 MHz. Picture pre-/post-processing. Ultra-low power implementation. This list of codecs is non-exhaustive, and is a baseline for the SVA performances. 2.2 Smart audio accelerator (SAA) This high-performance block is a flexible sophisticated audio accelerator based on the MMDSP+ programmable audio DSP, clocked up to 166 MHz, and features: 24-bit data path, ultra-low power implementation. The audio accelerator handles: Speech and audio codecs: AMR (WB, NR), MP3, AAC, WMA and more, Sample-rate conversion to 8, 16, 32, 44.1 and 48 khz, Extension of sound field and 3-D surround effects, Noise reduction and echo cancelling. 10/22 Architecture overview 2.3 Smart imaging accelerator (SIA) The smart imaging accelerator is provided by the image preprocessing module of the SVA. This flexible imaging engine provides real-time, programmable image processing, and features: Shot-to-shot performance (with CMOS sensor): 3 Mpixel, up to 15 image/s, 5 Mpixel, up to 9 image/s. Direct support for smart sensors (CMOS/CCD modules), unlimited resolution (YUV input with JPEG compression). Image reconstruction up to 80 Mpixel/s with raw Bayer input. With shutter, maximum sensor resolution depends on external SDRAM size and on target shot-to-shot delay. Auto-focus control, auto exposure control. Automatic white balance, contrast enhancement, brightness control. On-the-fly zoom, flash-gun control. Noise reduction, gamma correction, image sharpening. Ultra-low power implementation. 2.4 Smart graphics accelerator (SGA) The smart graphics accelerator provides an efficient 2D and 3D drawing tool that enables next generation of games and user interfaces while minimizing power consumption. 2D features ROP4. Line drawing. Triangle and rectangle fill. Alpha blending bit blit. Stretch/scale/rotate/mirror bit blit. Gradient color fill (horizontal and vertical). Full picture anti-aliasing filter. Image resizing. Font-expansion and anti-aliasing text drawing. 3D features Texture mapping. Texture transparency/blending/clamping/wrapping/mirroring. Flat and Gouraud shading. 16-bit Z buffering. Fog and depth cueing. Embossed bump mapping texture generation. 11/22 Architecture overview STn8815P Advanced power management unit (PMU) The dynamic PMU optimizes power consumption of the STn8815P14. It delivers all the platform clocks, and handles reset management. It also manages GPIO levels during sleep mode and emergency self-refresh of SDRAM. The PMU controls the external voltage regulator, in order to change its settings in different modes. In deep-sleep mode, only GPIOs, real-time clock (RTC), system and reset controller (SRC), PMU and secured RAM remain in operation. Voltage scaling supports two modes: standard 1.2 V and overdrive 1.4 V. The family of power manager ICs, STw481x companion chips, seamlessly interface with the Nomadik STn8815P14 and optimize global system power consumption leveraging on the PMU. 2.6 ARM926EJ processor The STn8815P14 CPU is an ARM926EJ reduced instruction set computer (RISC) processor. This 32-bit processor core supports 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density. The cached ARM CPU features a memory management unit (MMU) and is clocked at a frequency up to 350 MHz. It has a 16-Kbyte instruction cache, a 16-Kbyte data cache, and a 128-Kbyte level 2 cache, and supports the Jazelle extensions for Java acceleration. It also includes an embedded trace module (ETM Medium+) for real-time CPU activity tracing and debugging. It supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode, with normal or half-rate clock. 2.7 Embedded memory units 32 Kbytes of public ROM (for boot purposes), 64 Kbytes of secured ROM (for security purposes), 512 Kbytes of public RAM, 16 Kbytes of secured RAM (for security code and/or data), 1 Kbyte backup. 2.8 Advanced security The device contains 64 Kbytes of ROM and 16 Kbytes of RAM that
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