ELEC 5200/6200 Computer Architecture and Design Review of VHDL

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ELEC 5200/6200 Computer Architecture and Design Review of VHDL. Nitin Yogi 01/09/2008 Course Website http://www.eng.auburn.edu/~vagrawal/COURSE/E6200_Spr08/course.html. HDLs in Digital System Design. Model and document digital systems Hierarchical models
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ELEC 5200/6200 Computer Architecture and DesignReview of VHDL Nitin Yogi 01/09/2008 Course Website http://www.eng.auburn.edu/~vagrawal/COURSE/E6200_Spr08/course.html From Prof. Nelson's and Prof. Stroud's course material HDLs in Digital System Design
  • Model and document digital systems
  • Hierarchical models
  • System, RTL (Register Transfer Level), gates
  • Different levels of abstraction
  • Behavior, structure
  • Verify circuit/system design via simulation
  • Synthesize circuits from HDL models
  • From Prof. Nelson's and Prof. Stroud's course material Hardware Description Languages
  • VHDL = VHSIC Hardware Description Language (VHSIC = Very High Speed Integrated Circuits)
  • Developed by DOD from 1983 – based on ADA
  • IEEE Standard 1076-1987/1993/200x
  • Based on the ADA language
  • Verilog – created in 1984 by Philip Moorby of Gateway Design Automation (merged with Cadence)
  • IEEE Standard 1364-1995/2001/2005
  • Based on the C language
  • IEEE P1800 “System Verilog” in voting stage & will be merged with 1364
  • From Prof. Nelson's and Prof. Stroud's course material Other VHDL Standards
  • 1076.1–1999: VHDL-AMS (Analog & Mixed-Signal Extensions)
  • 1076.2–1996: Std. VHDL Mathematics Packages
  • 1076.3-1997: Std. VHDL Synthesis Packages
  • 1076.4-1995: Std. VITAL Modeling Specification (VHDL Initiative Towards ASIC Libraries)
  • 1076.6-1999: Std. for VHDL Register Transfer Level (RTL) Synthesis
  • 1164-1993: Std. Multivalue Logic System for VHDL Model Interoperability
  • From Prof. Nelson's and Prof. Stroud's course material Anatomy of a VHDL model
  • “Entity” describes the external view of a design/component
  • “Architecture” describes the internal behavior/structure of the component
  • Example: 1-bit full adder
  • A B Cin Full Adder Sum Cout From Prof. Nelson's and Prof. Stroud's course material Entity Inputs/Outputs
  • External view comprises input/output signals (“ports”)
  • A “port” is defined by its signal name, direction and type: port_name: direction data_type;
  • direction:
  • in - driven into the entity from an external source
  • out - driven from within the entity
  • inout - bidirectional – drivers within the entity and external
  • data_type: any scalar or aggregate signal type
  • From Prof. Nelson's and Prof. Stroud's course material Built-in Data Types
  • Scalar (single-value) signal types:
  • bit - values are ‘0’ or ‘1’
  • boolean – values are TRUE and FALSE
  • integer
  • Aggregate (multi-value) signal types:
  • bit_vector – array of bitssignal b: bit_vector(7 downto 0);signal c: bit_vector(0 to 7);
  • From Prof. Nelson's and Prof. Stroud's course material IEEE Standard 1164 Data Types
  • Type std_logic data values: ‘U’, ‘X’ – uninitialized/unknown‘0’, ‘1’ – strongly-driven 0/1‘L’, ‘H’ – weakly-driven 0/1 (resistive)‘Z’, ‘W’ - strong/weak “floating”‘-’ - don’t care
  • Type std_logic_vector is array of std_logic
  • Include package:library IEEE;use IEEE.std_logic_1164.all;
  • From Prof. Nelson's and Prof. Stroud's course material User-Defined Data Types
  • Any abstract data type can be created
  • Examples: type mnemonic is (add,sub,mov,jmp); signal op: mnemonic; type byte is array(0 to 7) of bit; signal dbus: byte;
  • From Prof. Nelson's and Prof. Stroud's course material entity format entity entity_name is generic(generic_name: type :=default_value; … generic_name: mode signal_type); port(signal_name: mode signal_type; … signal_name: mode signal_type); end entity entity_name; From Prof. Nelson's and Prof. Stroud's course material entity example (1-Bit Full Adder) entity full_add1 is port (-- I/O ports a: in bit; -- addend input b: in bit;-- augend input cin: in bit;-- carry input sum: out bit;-- sum output cout: out bit);-- carry output end full_add1 ; From Prof. Nelson's and Prof. Stroud's course material architecture format architecture architecture_name of entity_name is -- data type definitions (ie, states, arrays, etc.) -- internal signal declarations -- component declarations -- function and procedure declarations begin -- behavior of the model is described here using: -- component instantiations -- concurrent statements -- processes end architecture architecture_name; From Prof. Nelson's and Prof. Stroud's course material architecture example(behavioral) architecture dataflow of full_add1 is begin sum <= a xor b xor cin after 1 ns; cout <= (a and b) or (a and cin) or (b and cin) after 1 ns; end; From Prof. Nelson's and Prof. Stroud's course material Example using an internal signal architecture dataflow of full_add1 is signal x1: bit;-- internal signal begin x1 <= a xor b after 1 ns; sum <= x1 xor cin after 1 ns; cout <= (a and b) or (a and cin) or (b and cin) after 1 ns; end; From Prof. Nelson's and Prof. Stroud's course material Event-Driven Simulation Example a <= b after 1ns; c <= a after 1ns; Time a b c T ‘0’ ‘0’ ‘0’ T+1 ‘0’ ‘1’ ‘0’ - external event on b T+2 ‘1’ ‘1’ ‘0’ - resulting event on a T+3 ‘1’ ‘1’ ‘1’ - resulting event on c From Prof. Nelson's and Prof. Stroud's course material A X1 Sum Cin architecture example(Structural ) architecture structure of full_add1 is component xor-- declare component to be used port (x,y: in bit; z: out bit); end component; signal x1: bit;-- signal internal to this component begin G1: xor port map (a, b, x1);-- instantiate 1st xor gate G2: xor port map (x1, cin, sum); -- instantiate 2nd xor gate …add circuit for carry output… end; From Prof. Nelson's and Prof. Stroud's course material Example: D flip-flop entity DFF is port (Preset: in bit; Clear: in bit; Clock: in bit; Data: in bit; Q: out bit; Qbar: out bit); end DFF; Data Clock Preset Q Qbar Clear From Prof. Nelson's and Prof. Stroud's course material 7474 D flip-flop equations architecture eqns of DFF is signal A,B,C,D: bit; signal QInt, QBarInt: bit; begin A <= not (Preset and D and B) after 1 ns; B <= not (A and Clear and Clock) after 1 ns; C <= not (B and Clock and D) after 1 ns; D <= not (C and Clear and Data) after 1 ns; Qint <= not (Preset and B and QbarInt) after 1 ns; QBarInt <= not (QInt and Clear and C) after 1 ns; Q <= QInt; QBar <= QBarInt; end; From Prof. Nelson's and Prof. Stroud's course material D(3) D(2) D(1) D(0) 4-bit Register (Structural Model) entity Register4 is port ( D: in bit_vector(0 to 3); Q: out bit_vector(0 to 3); Clk: in bit; Clr: in bit; Pre: in bit); end Register4; CLK PRE CLR Q(0) Q(1) Q(2) Q(3) From Prof. Nelson's and Prof. Stroud's course material Register Architecture architecture structure of Register4 is component DFF-- declare library component to be used port (Preset: in bit; Clear: in bit; Clock: in bit; Data: in bit; Q: out bit; Qbar: out bit); end component; signal Qbar: bit_vector(0 to 3); -- dummy for unused FF output begin -- Signals connected to ports in order listed above F3: DFF port map (Pre, Clr, Clk, D(3), Q(3), Qbar(3)); F2: DFF port map (Pre, Clr, Clk, D(2), Q(2), Qbar(2)); F1: DFF port map (Pre, Clr, Clk, D(1), Q(1), Qbar(1)); F0: DFF port map (Pre, Clr, Clk, D(0), Q(0), Qbar(0)); end; From Prof. Nelson's and Prof. Stroud's course material Register Architecture(short cut – “generate” statement) begin for k in 0 to 3 generate F: DFF port map (Pre, Clr, Clk, D(k), Q(k), Qbar(k)); end generate; end;
  • Generates multiple copies of the given statement(s)
  • Value of k inserted where specified
  • Iteration number k is appended to each label F
  • Result is identical to previous example
  • From Prof. Nelson's and Prof. Stroud's course material Statements used for modeling
  • Concurrent statements
  • Concurrent assignments
  • when – else
  • with – select – when
  • Sequential statements using “process”
  • if – then – else
  • case – when
  • for – loop
  • while - loop
  • From Prof. Nelson's and Prof. Stroud's course material Concurrent assignments A <= not (Preset and D and B) after 1 ns; B <= not (A and Clear and Clock) after 1 ns; C <= not (B and Clock and D) after 1 ns; D <= not (C and Clear and Data) after 1 ns; From Prof. Nelson's and Prof. Stroud's course material With – select - when with S select y <= a after 1 ns when “00”, b after 1 ns when “01”, c after 1 ns when “10”, d after 1 ns when “11”; (0r: d after 1 ns when others;) 4-to-1 Mux 00 01 10 11 a b c d y S From Prof. Nelson's and Prof. Stroud's course material When - else y <= a after 1 ns when (S=“00”) else b after 1 ns when (S=“01”) else c after 1 ns when (S=“10”) else d after 1 ns; Any boolean expression can be used for each condition. Ex. y <= a after 1 ns when (F=‘1’) and (G=‘0’) … 4-to-1 Mux 00 01 10 11 a b c d y S From Prof. Nelson's and Prof. Stroud's course material a y en Tristate buffer example library ieee; use ieee.std_logic_1164.all; entity tristate is port ( a: in bit; y: out std_logic; en: in bit); end tristate; architecture a1 of tristate is begin y <= a after 1 ns when (en=‘1’) else ‘Z’ after 1 ns; end; -- Error: Type mismatch between y and a From Prof. Nelson's and Prof. Stroud's course material a y en Tristate buffer example(correct) library ieee; use ieee.std_logic_1164.all; entity tristate is port ( a: in bit; y: out std_logic; en: in bit); end tristate; architecture a1 of tristate is begin y <= ‘0’ after 1 ns when (en=‘1’) and (a=‘0’) else ‘1’ after 1 ns when (en=‘1’) and (a=‘1’) else ‘Z’ after 1 ns; end; From Prof. Nelson's and Prof. Stroud's course material a y en Tristate bus buffer example library ieee; use ieee.std_logic_1164.all; entity tristate is port ( a: in bit_vector(0 to 7); y: out std_logicvector(0 to 7); en: in bit); end tristate; architecture a1 of tristate is begin y <= to_stdlogicvector(a) after 1 ns when (en=‘1’) else “ZZZZZZZZ” after 1 ns; end; From Prof. Nelson's and Prof. Stroud's course material VHDL “Process” Construct
  • Allows conventional programming language methods to describe circuit behavior
  • Supported language constructs (“sequential statements”) –only allowed within a process:
  • variable assignment
  • if-then-else (elsif)
  • case statement
  • while (condition) loop
  • for (range) loop
  • From Prof. Nelson's and Prof. Stroud's course material Process Format [label:] process (sensitivity list) declarations begin sequential statements end process;
  • Process statements executed once at start of simulation
  • Process halts at “end” until an event occurs on a signal in the “sensitivity list”
  • From Prof. Nelson's and Prof. Stroud's course material D Q CLK Using a “process” to model sequential behavior entity DFF is port (D,CLK: in std_logic; Q: out std_logic); end DFF; architecture behave of DFF is begin process(clk) -- “process sensitivity list” begin if (clk’event and clk=‘1’) then Q <= D after 1 ns; end if; end process; end;
  • Process statements executed sequentially (sequential statements)
  • clk’event is an attribute of signal clk which is TRUE if an event has occurred on clk at the current simulation time
  • From Prof. Nelson's and Prof. Stroud's course material D Q CLK Alternative to sensitivity list entity DFF is port (D,CLK: in std_logic; Q: out std_logic); end DFF; architecture behave of DFF is begin process -- no “sensitivity list” begin wait on clk; -- suspend process until event on clk if (clk=‘1’) then Q <= D after 1 ns; end if; end process; end;
  • Other “wait” formats: wait until (clk’event and clk=‘1’) wait for 20 ns;
  • Process executes endlessly if no sensitivity list or wait statement!
  • From Prof. Nelson's and Prof. Stroud's course material D latch vs. D flip-flop entity Dlatch is port (D,CLK: in std_logic; Q: out std_logic); end Dlatch; architecture behave of Dlatch is begin process(D, clk) begin if (clk=‘1’) then Q <= D after 1 ns; end if; end process; end; For latch, Q changes whenever the latch is enabled by CLK=‘1’ (rather than being edge-triggered) D Q CLK From Prof. Nelson's and Prof. Stroud's course material CLR D Q CLK PRE Synchronous vs. Asynchronous Flip-Flop Inputs entity DFF is port (D,CLK: in std_logic; PRE,CLR: in std_logic; Q: out std_logic); end DFF; architecture behave of DFF is begin process(clk,PRE,CLR) begin if (CLR=‘0’) then -- CLR has precedence Q <= ‘0’ after 1 ns; elsif (PRE=‘0’) then -- Then PRE has precedence Q <= ‘1’ after 1 ns; elsif (clk’event and clk=‘1’) then Q <= D after 1 ns; -- Only if CLR=PRE=‘1’ end if; end process; end; From Prof. Nelson's and Prof. Stroud's course material Configurable N-bit register entity REG is generic (N:integer := 4) port (D,CLK: in std_logic_vector(N-1 downto 0); Q: out std_logic_vector(N-1 downto 0)); end REG; architecture behave of REG is begin process(clk) begin if (clk’event and clk=‘1’) then Q <= D after 1 ns; end if; end process; end; From Prof. Nelson's and Prof. Stroud's course material Using a “variable” to describe sequential behavior within a process cnt: process(clk) variable count: integer; -- internal counter state begin -- valid only in a process if clk=‘1’ and clk’event then if ld=‘1’ then -- “to_integer” must be supplied count := to_integer(Din); elsif cnt=‘1’ then count := count + 1; end if; end if; -- “to_bitvector” must be supplied Dout <= to_bitvector(count); end process; From Prof. Nelson's and Prof. Stroud's course material Modeling Finite State Machines (Synchronous Sequential Circuits) Comb. Logic Inputs x Outputs z Present State y Next State Y FFs Clock Next State Y = f(x,y) From Prof. Nelson's and Prof. Stroud's course material Synchronous Sequential Circuit (FSM) Example From Prof. Nelson's and Prof. Stroud's course material FSM Example – entity definition entity seqckt is port ( x: in bit;-- FSM input z: out bit;-- FSM output clk: in bit );-- clock end seqckt; From Prof. Nelson's and Prof. Stroud's course material FSM Example - behavioral model architecture behave of seqckt is type states is (A,B,C); -- symbolic state names signal curr_state,next_state: states; begin -- Model the memory elements of the FSM process (clk) begin if (clk’event and clk=‘1’) then pres_state <= next_state; end if; end process; (continue on next slide) From Prof. Nelson's and Prof. Stroud's course material FSM Example - continued -- Model the next-state and output functions of the FSM process (x, pres_state) -- function inputs begin case pres_state is -- describe each state when A => if (x = ‘0’) then z <= ‘0’; next_state <= A; else -- (x = ‘1’) z <= ‘0’; next_state <= B; end if; (continue next slide for pres_state = B and C) From Prof. Nelson's and Prof. Stroud's course material FSM Example (continued) when B => if (x=‘0’) then z <= ‘0’; next_state <= A; else z <= ‘1’; next_state <= C; end if; when C => if (x=‘0’) then z <= ‘0’; next_state <= C; else z <= ‘1’; next_state <= A; end if; end case; end process; end; From Prof. Nelson's and Prof. Stroud's course material 64K x 8 Memory Example library ieee; use ieee.std_logic_1164.all; use work.qsim_logic.all;-- package with to_integer() func entity memory8 is port (dbus: inout std_logic_vector(0 to 7); abus: in std_logic_vector(0 to 15); ce: in bit;-- active low chip enable oe: in bit;-- active low output enable we: in bit);-- active low write enable end memory8; From Prof. Nelson's and Prof. Stroud's course material 64K x 8 Memory Example architecture reglevel of memory8 is begin process (ce,oe,we,abus,dbus) type mem is array(natural range <>) of std_logic_vector(0 to 7); variable M: mem(0 to 65535); begin if (ce='0') and (oe='0') then -- read enabled dbus <= M(to_integer(abus));-- drive the bus elsif (ce='0') and (we='0') then -- write enabled dbus <= "ZZZZZZZZ";-- disable drivers M(to_integer(abus)) := dbus;-- write to M else dbus <= "ZZZZZZZZ";--disable drivers end if; end process; end; From Prof. Nelson's and Prof. Stroud's course material Miscellaneous VHDL Items
  • Subtypes of previously-defined data types subtype int3 is integer range 0 to 7;
  • Use of “alias” for existing elements signal instruc: bit_vector(0 to 31); alias opcode: bit_vector(0 to 5) is instruc(0 to 5); alias rd: bit_vector(0 to 4) is instruc(6 to 10); alias rs: bit_vector(0 to 4) is instruc(11 to 15);
  • Fill a bit_vector with a constant (right-most bits): A <= (‘0’,’1’,’1’, others => ‘0’); B(15 downto 0) <= C(15 downto 0); B(31 downto 16) <= (others => C(15)); -- sign extension!
  • Concatenate bits and bit_vectors A <= B & C(0 to 3) & “00”; -- A is 16 bits, B is 10 bits
  • From Prof. Nelson's and Prof. Stroud's course material Unconstrained Bit Vectors
  • Allows a generic component with different sizes: entity mux is port (a,b: in bit_vector; -- unconstrained c: out bit_vector; s: in bit ); end mux; architecture x of mux is begin c <= a when (s=‘0’) else b; end;
  • From Prof. Nelson's and Prof. Stroud's course material Unconstrained Bit Vectors
  • Vector constrained when instantiated: signal s1,s2: bit; signal a5,b5,c5: bit_vector (0 to 4); signal a32,b32,c32: bit_vector (0 to 31); component mux port (a,b: in bit_vector; -- unconstrained c: out bit_vector; s: in bit ); end component; begin M5: mux port map (a5,b5,c5,s1); -- 5-bit mux M32: mux port map (a32,b32,c32,s2); -- 32-bit mux
  • From Prof. Nelson's and Prof. Stroud's course material
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