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Experiment 6 ADDRESSING MODES AND SEQUENCE GENERATION
Aim:
a) To learn the following addressing modes of TMS320C54X DSP. i) immediate ii) direct addressing iii) indirect addressing : general type, indexing, circular addressing iv) memory mapped register addressing b) To generate and find the sum of the following arithmetic sequences.
i) 1+2+3+4+ …+ n
ii) 1-2+3-
4+ …+ n
iii) 1
2
+2
2
+3
2
+…+ n
2
iv) 1+1+2+3+5+8 …+ n (Fibonacci series)
The value of n is defined as variable assignment in the program
Objectives:
1. To understand the data load and store operations and various addressing modes of TMS320C54X DSP. 2. To make familiar the assembly instructions for arithmetic and logical operations. 3. To understand the branch instructions suitable to define loop functions
Algorithm: a) Addressing modes
i) Immediate addressing mode: Write the various arithmetic, logic instructions, load and store instructions that support short and long immediate addressing mode. ii) Direct addressing mode: Write the various arithmetic, logic instructions, load and store instructions that direct addressing mode with DP. iii) Indirect addressing mode: Write the various arithmetic, logic instructions load and store instructions that support various indirect addressing mode. iv) Memory mapped register addressing mode: Write the assembly instructions to access memory mapped registers using various addressing modes and memory mapped register addressing mode. (Example use
–
AR0, DP and BK registers)
b) Sequence generation
i) 1+2+3+4+ …+ n
Start Read n Sum = 0 i=1
for i=1: n Begin Store i in memory Sum=Sum+i 3 Increment i by 1 End Store Sum in memory Stop
ii) 1-2+3-
4+ …+ n
Start Read n Sum = 0, Sum1 = 0, Sum2 =0, i=1 for i=1: n Begin Store i in memory If i is odd Sum1=Sum1+i Else Sum2=Sum2+i Increment i by 1 Sum = Sum1+negative of (Sum2) End Store Sum in memory Stop
iii) 1
2
+2
2
+3
2
+...+n
2
Start Read n Sum = 0, i=1 to n, a=0 for i=1:n Begin Store i in the memory a=i*i Store a in memory Sum=Sum+a End Store Sum in the memory End
iv) 1+1+2+3+5+8 …+ n (Fibonacci series)
Start Read n a=0, b=1 Store a and b in the memory for i=1: n-2 Begin c=a
a=a+b b=c Store a in the memory 4 End Stop
Assembly Language Codes and Observations: (i) Addressing Modes:
.mmregs .text LD #05,A STL A,BK LD #10,A STL A,AR3 STL A,10H LD #1080h,A STL A,AR2 LD #0h,A Loop ADD *AR2+%,A ADD *AR2+%,A ADD *AR2+%,A ADD *AR2+%,A ADD *AR2+%,A BANZ Loop,*AR3- .end
(ii) Sequence Generation (a) 1+2+3+...+n
.mmregs .text LD #09H,A STL A,AR3 LD #00h,A LD #01h,B ST #1000H,AR6 Loop STL B,*AR6+ ADD B,A ADD #1h,B BANZ Loop,*AR3- STL A,*AR6 .end
(b)
1-2+3-
4+ …+ n
.mmregs .text LD #0,B LD #4,A STL A,AR3 LD #1,A STL A,AR5 LD #1,A ST #2000H,AR2 Loop STL A,*AR2+ ADD A,B ADD AR5,A SUB A,B ADD AR5,A BANZ Loop,*AR3- STL B,*AR2 .end
(c) 1
2
+2
2
+3
2
+...+n
2
.mmregs .text LD #04H,A STL A,AR3 LD #01h,A STL A,T LD #00h,A LD #01,B

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