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    ASM Chart: Multiplier Control COE608: Computer Organization and Architecture Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan    Electrical and Computer Engineering    Ryerson University   Overview ã Types of Sequential Circuits ♦ Mealy and Moore Machine Models ♦ Sequence Detector Implementations ã Algorithmic State Machines: Introduction ã Realization of ASM ã Control Unit Design of the Multiplier ã Hardwired Control ♦ Sequence Register and Decoder Method ♦ One Flip-Flop per State Method Part of Chapter 8 , s ection 8.3 - 8.5 of Text by Mano and Kime ©  G.Khan Computer Organization & Architecture-COE608: ASM and Control Page: 1    Sequential Logic Circuits } Output variables (z 1  ..... z m ) Nv } ext-state ariables (Y 1  ..... Y r  )Primary input variables (x 1  ..... x n  )   Present state variables (y 1 ..... y r  ) { { MemoryDevices Clock CombinationalLogic Inputs Primary Inputs State variables Outputs Output variables  Next state variables. Synchronous Sequential Circuits Clock is used to ensure occurrence of event (change of state) at a specified instant of time. Asynchronous Sequential Circuits ©  G.Khan Computer Organization & Architecture-COE608: ASM and Control Page: 2      Sequential Machine Models Main Models of Sequential Circuits or Machines are: Mealy and Moore Model Mealy Machines: Their outputs depend on both the present state and the present inputs. Moore Machines: The outputs depend on the  present state only. PresentState Inputs  x   Outputs (Z) Clock   Next State   Comb. Logic  Network State Reg.   PresentState Inputs  x   Outputs(Z) Next State Comb. Logic  Network    State Reg.   Clock    ©  G.Khan Computer Organization & Architecture-COE608: ASM and Control Page: 3    Sequential Machine Models Mealy Model Moore Model   10/0 01/0 10/0 00/0 11/1 01/010/000/1 11/0 01/000/0 11/0 AB/S Z Y X 10 01 10 00 11 01 10 00 11 01 00 11 AB Z/0Y/1X/0 PS NS   PS NS Output   AB 00 01 11 10  AB  00 01 11 10 S x x/0 z/0 x/0 y/0xx z x y 0 y x/0 y/0 x/1 y/0yx y x y 1 z x/1 z/0 x/0 z/0zx z x z 0 Mealy State Table Moore State Table ©  G.Khan Computer Organization & Architecture-COE608: ASM and Control Page: 4  
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