An Example of ASM Design: A Binary Multiplier - PDF

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A Example of ASM Desig: A Biary Multiplier Itroductio Dr. D. Capso Electrical ad Computer Egieerig McMaster Uiversity A algorithmic state machie (ASM) is a Fiite State Machie that uses a sequetial circuit
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A Example of ASM Desig: A Biary Multiplier Itroductio Dr. D. Capso Electrical ad Computer Egieerig McMaster Uiversity A algorithmic state machie (ASM) is a Fiite State Machie that uses a sequetial circuit (the Cotroller) to coordiates a series of operatios amog other fuctioal uits such as couters, registers, adders etc. (the Datapath). The series of operatios implemet a algorithm. The Cotroller passes cotrol sigals which ca be Moore or Mealy outputs from the Cotroller, to the Datapath. The Datapath returs iformatio to the Cotroller i the form of status iformatio that ca the be used to determie the sequece of states i the Cotroller. Both the Cotroller ad the Datapath may each have exteral iputs ad outputs ad are clocked simultaeously as show i the followig figure: Iputs Outputs Iputs Cotroller Status Cotrol Datapath clock Outputs Thik about this: A microprocessor may be cosidered as a (large!) ASM with may iputs, states ad outputs. A program (ay software) is really just a method for specificatio of its iitial state The two basic strategies for the desig of a cotroller are: 1. hardwired cotrol which icludes techiques such as oe-hot-state (also kow as oe flipflop per state ) ad decoded sequece registers. 2. microprogrammed cotrol which uses a memory device to produce a sequece of cotrol words to a datapath.. Sice hardwired cotrol is, geerally speakig, fast compared with microprogrammig strategies, most moder microprocessors icorporate hardwired cotrol to help achieve their high performace (or i some cases, a combiatio of hardwired ad microprogrammed cotrol). The early geeratios of microprocessors used microprogrammig almost exclusively. We will discuss some basic cocepts i microprogrammig later i the course for ow we cocetrate o a desig example of hardwired cotrol. The ASM we will desig is a -bit usiged biary multiplier. Biary Multiplicatio The desig of biary multiplicatio strategies has a log history. Multiplicatio is such a fudametal ad frequetly used operatio i digital sigal processig, that most moder DSP chips have dedicated multiplicatio hardware to maximize performace. Examples are filterig, codig ad compressio for telecommuicatios ad cotrol applicatios as well as may others. Multiplier uits must be fast! The first example that we cosidered (i class) that used a repeated additio strategy is ot always fast. I fact, the time required to multiply two umbers is variable ad depedet o the value of the multiplier itself. For example, the calculatio of 5 x 9 as requires more clock pulses tha the calculatio of 5 x 3 = The larger the multiplier, the more iteratios that are required. This is ot practical. Thik about this: How may iteratios are required for multiplyig say, two 16-bit umbers, i the worst case? Aother approach to achieve fast multiplicatio is the look-up table (LUT). The multiplier ad multiplicad are used to form a address i memory i which the correspodig, pre-computed value of the product is stored. For a -bit multiplier (that is, multiplyig a -bit umber by a -bit umber), a (2 + x 2)-bit memory is required to hold all possible products. For example, a 4-bit x 4-bit multiplier requires (2 8 ) x 8 = 2048 bits. For a 8-bit x 8-bit multiplier, a (2 8+8 ) x 16 = 1 Mbit memory is required. This approach is coceptually simple ad has a fixed multiply time equal to the access time of the memory device, regardless of the data beig multiplied. But it is also impractical for larger values of. Thik about this: What memory capacity is required for multiplyig two 16-bit umbers? Two 32-bit umbers? Most multiplicatio hardware uits use iterative algorithms implemeted as a ASM for which the worst-case multiplicatio time ca be guarateed. The algorithm we preset here is similar to the pecil-ad-paper techique that we aturally use for multiplyig i base 10. Cosider the followig example: 123 (the multiplicad) x 432 (the multiplier) (1 st partial product) 369 (2 d partial product) 492 (3rd partial product) (the product) Each digit of the multiplier is multiplied by the multiplicad to form a partial product. Each partial product is shifted left (that is, multiplied by the base) by the amout equal to the power of the digit of the correspodig multiplier. I the example above, 246 is actually 246x10 0, 369 is 369x10 1 = 3690 ad 492 is actually 492x10 2 = 49200, etc. There are as may partial products as there are digits i the multiplier. Biary multiplicatio ca be doe i exactly the same way: 1100 (the multiplicad) x 1011 (the multiplier) 1100 (1 st partial product) 1100 (2d partial product) 0000 (3rd partial product) 1100 (4th partial product) (the product) However, with biary digits we ca make some importat observatios: - Sice we multiply by oly 1 or 0, each partial product is either a copy of the multiplicad shifted by the appropriate umber of places, or, it is 0. - The umber of partial products is the same as the umber of bits i the multiplier - The umber of bits i the product is twice the umber of bits i the multiplicad. Multiplyig two -bit umbers produces a 2-bit product. We could the desig datapath hardware usig a 2-bit adder plus some other compoets (as i the example of Figure of Brow ad Vraesic) that emulates this maual procedure. However, the hardware requiremet ca be reduced by cosiderig the multiplicatio i a differet light. Our algorithm may be iformally described as follows. Cosider each bit of the multiplier from right to left. Whe a bit is 1, the multiplicad is added to the ruig total that is the shifted right. Whe the multiplier bit is 0, o add is ecessary sice the partial product is 0 ad the oly the shift takes place. After cycles of this strategy (oce for each bit i the multiplier) the fial aswer is produced. Cosider the previous example agai: 1100 (the multiplicad) x 1011 (the multiplier) 0000 (iitial partial product, start with 0000) 1100 (1 st multiplier bit is 1, so add the multiplicad) 1100 (sum) (shift sum oe positio to the right) 1100 (2 d multiplier bit is 1, so add multiplicad agai) (sum, with a carry geerated o the left) (shift sum oce to the right, icludig carry) (3rd multiplier bit is 0, so skip add, shift oce) 1100 (4th multiplier bit is 1, so add multiplicad agai) (sum, with a carry geerated o the left) (shift sum oce to the right, icludig carry) Notice that all the adds take place i these 4 bit positios we eed oly a 4-bit adder! We also eed shiftig capability to capture the bits movig to the right as well as a way to store the carries resultig from the additios. The fial aswer (the product) cosists of the accumulated sum ad the bits shifted out to the right. A hardware desig that ca implemet this algorithm is described i the ext sectio. Desig of the Biary Multiplier Datapath The multiplicatio as described above ca be implemeted with the compoets as show i the figure o the ext page (ote that for simplicity, the clock iputs are ot show). It is the role of the cotroller to provide a sequece of the iputs to each compoet to cause the datapath hardware to perform the desired operatios. Registers A ad Q are cotrolled with sychroous iputs Load (parallel load), Shift (shift oe positio to the right with left serial iput) ad Clear (force the cotets to 0). The D flipflop has a asychroous Clear iput ad the couter has a asychroous iput Iit (force the cotets to 11..1). The log 2 -bit couter (Couter P) is used to keep track of the umber of iteratios (). Couter P is loaded with the value -1 ad couts dow to zero - thus operatios are esured. Each operatio is either (a) add the shift or (b) just shift as described i the multiply algorithm above. Zero detectio o the couter produces a output Z that is HI whe the couter hits zero ad this is used to tell the cotroller that the sequece is complete. The Couter P is iitialized to -1 with iput Iit = 1. The multiplicad is applied to oe -bit iput of the adder. The sum output from the adder is stored as a parallel load ito Register A. Register A ca also shift to the right, acceptig a 1-bit serial iput from the left. This is provided from the output of a D flip flop which stores the value of the carry out from the adder i the previous additio. Register Q receives its left serial iput whe shiftig from the right-most bit (lsb) of Register A. Register A ad Q are idetical i operatio (but cotrolled differetly) ad together with the carry flipflop, they form a (1 + + )-bit shift register. That is, Registers C, A ad Q are coected such that the carry value stored i the flipflop eters Register A from the left ad the bit shifted out from the right of Register A eters Register Q from its left. At the ed of the process, registers A ad Q will hold the 2-bit product (the msb s are i Register A). The multiplier is iitially stored i Register Q via its parallel load capability. The reaso for this is that it provides a coveiet way to access each bit of the multiplier i successio at the lsb positio (Q 0 ) of Register Q. I the multiply algorithm, each bit of the multiplier is used to decide if there should be a (a) add with shift or (b) shift oly. So, Q 0 is used to tell the cotroller which of these operatios to perform o each iteratio. After each shift, oe bit of the multiplier is lost to the right ad the Product shifts ito Register Q from the left. After shifts, Register Q holds the lsb s of the product ad the Multiplier is totally lost. Puttig the datapath circuit for the biary multiplier ito a box, we see it has: Data Iputs: Data Outputs: Multiplicad ( bits) Multiplier ( bits) Product (2 bits) Cotrol iputs: Clear carry Load, Shift ad Clear (for each shift register) Iit (for the couter) Status outputs: Z (zero detect) ad Q 0 (each bit of the Multiplier, i successio) Multiplicad Multiplier - 1 log 2 0 C i A B C out SUM Parallel Adder Biary Dow Couter Couter P Iit Z (Zero Detect) Flipflop Shift Reg Shift Reg D Q C Clear Left serial iput Register A Load Shift Clear Left serial iput Register Q Load Shift Clear 1 1 (lsb of Reg A) Q 0 (lsb of Reg Q) Product (msb's) Product (lsb's) Datapath for Biary Multiplier Desig of the Biary Multiplier Cotroller A ASM chart that implemets the biary multiply algorithm is give below. Note that idicates a assigmet, for example, C 0 meas set C to 0. 0 G 1 C «0, A «0, P «-1 Q «multiplier MUL0 0 Q 0 1 C «0 A «A + multiplicad C «Cout MUL1 C A Q «shr (C A Q) P «P-1 0 Z 1 The process is achieved with 3 states (, MUL0 ad MUL1). Each state will provide cotrol sigals to the Datapath to perform the multiplicatio sequece. The process is started with a iput G. As log as G remais LO, the ASM remais i state. Whe G=1, the multiplicatio process is started. As the ASM moves to state MUL0, the carry flip flop is cleared (C 0), Reg A is cleared (A 0), the Couter is preset to -1 (P -1) ad Register Q is loaded with the Multiplier. I state MUL0, the value of each bit of the multiplier (available o Q 0 ) determies if the multiplicad is added (Q 0 = 1) or ot (Q 0 =0). For the case Q 0 =0, the Carry flipflop is cleared ; for the case Q 0 =1, the C out from the adder is stored i the carry flipflop. The ext state is always MUL1. I MUL1, the Carry flipflop, Reg A ad Reg Q are treated as a (1 + + )-bit register ad shifted oe positio to the right, together. This is idicated with the otatio C A Q shr (C A Q) i the ASM chart. The couter is also decremeted (P P 1). The value of Z the determies whether to: retur to state MUL0 (Z=0) to cotiue iteratio OR retur to state (Z=1) thus completig the process. Remember that Z=1 meas that the couter has couted dow from -1 to 0 ad therefore iteratios have bee completed. State =0 therefore idicates that the Multiplier is curretly multiplyig ad whe the ASM returs to state (=1), it idicates that multiplicatio is completed. At this poit i the desig process, the cotrol sigals must be idetified ad their ames chose. This is doe by ispectio of the ASM chart ad the datapath circuit. I MUL0, the operatios P 1, A 0 ad Q multiplier are all idepedet of oe aother i the datapath ad thus ca be doe simultaeously ad therefore ca share a commo cotrol sigal (Iitialize). However, the operatio C 0 must have its ow cotrol sigal (Clear_C) sice it occurs i both states ad i MUL0. Operatios C Cout ad A A + multiplicad, required i state MUL0, ca share a cotrol sigal (Load) sice they are also idepedet fuctios i the datapath. Ad, similarly, the shiftig of registers C A Q ad decremetig of couter P ca share a commo cotrol sigal sice they are idepedet operatios i the datapath ad are required i state MUL1 (Shift_dec). The ames of the cotrol sigals are of course, a matter of desig choice. We ca summarize all the operatios that must take place o each compoet i the datapath ad idicate the correspodig cotrol sigal ames that should be passed to the datapath i the followig table: Datapath compoet Carry flipflop Couter P Register A Register Q Operatio C 0 C Cout (from the adder) P - 1 P P 1 A 0 A A + multiplicad C A Q shr (C A Q) Q multiplier C A Q shr (C A Q Cotrol Sigal ame Clear_C Load Iitialize Shift_dec Iitialize Load Shift_dec Iitialize Shift_dec The state trasitio diagram for the cotroller for this ASM is show below. Note that oly the iputs are show; the outputs are ot idicated: G=0 G=1 MUL0 z=0 MUL1 z=1 From ispectio of the state trasitio diagram, the iput equatios for the D flipflops (usig oe flipflop per state) are easily formed: D = G + MUL1 Z D MUL0 = G + MUL1 Z D MUL1 = MUL0 From the ASM chart ad the table above, the equatios for the cotrol sigals outputs from the cotroller are formed: Iitialize = G Clear_C = G + MUL0 Q 0 Load = MUL0 Q 0 Shift_dec = MUL1 Fially, to provide a mechaism to force the state machie to state (such as at power-up), a asychroous iput Reset_to_ is coected to the asychroous iputs of the flipflops. The circuit for the cotroller is the simply, a implemetatio of all of these equatios as follows: Cotroller for Biary Multiplier Go Reset_to_ D P Q Clock Iitialize Q 0 Clear_C D MUL0 Q Load C MUL0 Z MUL1 D Q C Shift_dec Our biary multiplier ASM has the form: Go Reset to Multiplicad Multiplier Cotroller Z, Q 0 Iitialize, Clear_C, Load, Shift_dec Datapath clock 2 Product Combiig the cotroller ad the datapath to form the top level of our desig, the biary multiplier may be viewed as: Multiplier Multiplicad Go Biary Multiplier 2 Product Reset to Clock Note that the state variable has bee brought to the top level sice it ca be use to idicate whe the Biary Multiplier is busy. The Go ad lies are called hadshakig lies ad are used to coordiate the operatio of the multiplier with the exteral world. If =1, a multiply ca be started by puttig the umbers to be multiplied o the Multiplier ad Multiplicad iputs ad settig Go=1 at which time the state machie jumps to state MUL0 (ad therefore, simultaeously, chages to 0) to start the process. Whe returs to 1, the aswer is available o the Product output ad aother multiplicatio could be started. No multiplicatio should be attempted while is 0. Coclusio This desig of a Biary Multiplier is valid for ay value of. For example, for =16, the multiplicatio of two 16-bit umbers, the datapath compoets would simply be exteded to accommodate 16 bits i Registers A ad Q ad the couter would require log 2 (16) = 4 bits. The adder would also be required to be 16-bits i width. However, the same cotroller implemetatio ca be used sice its desig is idepedet of. The multiplicatio time for =16 would be 2(16) + 1 = 33 clocks. The product would cotai 32 bits. Further refiemets ca be made to ehace the speed ad capability of the ASM. For example, i our algorithm, each 0 i the multiplier iput data causes a shift without a add, each takig a clock pulse. If the multiplier iput cotais rus of cosecutive 0 s, a barrel shifter could be used to implemet all of the required shifts (equal to the legth of the ru of 0 s) i a sigle clock. Thik about this: What modificatios to our desig would be required i order to be able to hadle siged umbers.? Example: Multiply 12 x 5 = 60 (with = 4) Assumig a 4-bit multiplier, i biary, this is 1100 x 0101 = The followig table summarizes all the values i the ASM for each step i this multiplicatio. The left colum represets each clock pulse applied to the multiplier. The multiplicatio time for this ASM is always 2+1 clocks (cofirm this with the state trasitio diagram). Sice =4, there are 9 clocks required to complete a multiplicatio. Multiplicatio time is ot data depedet as i our first example that used repeated additio! The first row of the table is the iitial state (state ) at which every multiply begis. The, for each clock pulse applied, we move dow oe row i the table. Couter P is this example has 2 bits (to cout 4 iteratios) ad the zero detect Z ca be see to be Z=1 oly whe Couter P couts dow to 00. The values of registers C, A ad Q are show for each clock pulse i the process. Note that the multiplier is iitially stored i Q, the shifted out to the right givig access to each bit i the multiplier at the Q 0 (lsb) positio. At the same time, the product shifts i from the left. The product is formed i registers A ad Q with the additio o each iteratio occurrig i Register A if the cotets of the lsb of Register Q is HI (i.e. Q 0 = 1). Notice that registers C, A ad Q are shifted o every iteratio ad that the fial aswer is cotaied i Registers A ad Q o the fial clock pulse. At this poit, we have retured to state idicatig that multiplicatio is complete. The curret state of the ASM is idicated with a 1 i the appropriate States colum. Note that sice we are usig oe flipflop per state, oly oe of the 3 colums ca cotai a 1; the others are of course, 0. I the Cotrol Sigals colums, the values for each cotrol sigal are provided for each clock pulse. Note that Iitialize, Clear_C ad Load are Mealy-type outputs sice they are a fuctio of both curret state ad iputs. Shift_dec is a Moore-type output sice it depeds oly o curret state (MUL1) ad is ot a fuctio of ay iput. I fact, Shift_dec = MUL1. Work through this example lie by lie to verify its operatio. Example: 12 x 5 Clock pulse Couter P Z C Reg A Reg Q States MUL0 Cotrol Sigals Iitialize Clear_C Load Shift_dec MUL x x x x x x x x x
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