24C02C. 2K 5.0V I 2 C Serial EEPROM. Package Types. Features. Block Diagram. Description

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2 5.0V I 2 erial EEROM 2402 Features ackage ypes ingle supply with operation from 4.5 to 5.5V Low-power MO technology - 1 m active current typical - 10 µ standby current typical at 5.5V Organized as a
2 5.0V I 2 erial EEROM 2402 Features ackage ypes ingle supply with operation from 4.5 to 5.5V Low-power MO technology - 1 m active current typical - 10 µ standby current typical at 5.5V Organized as a single block of 256 bytes (256 x 8) Hardware write protection for upper half of array 2-wire serial interface bus, I 2 compatible 100 khz and 400 khz compatibility age write buffer for up to 16 bytes elf-timed write cycle (including auto-erase) Fast 1 m write cycle time for Byte or age mode ddress lines allow up to eight devices on bus 1,000,000 erase/write cycles ED protection 4,000V Data retention 200 years 8-pin DI, OI or O packages vailable for extended temperature ranges DI/OI O Vss V Vcc W L D V W L D - ommercial (): 0 to Industrial (I): -40 to utomotive (E): -40 to +125 Description Block Diagram W HV Generator he Microchip echnology Inc is a 2 bit erial Electrically Erasable ROM with a voltage range of 4.5V to 5.5V. he device is organized as a single block of 256 x 8-bit memory with a 2-wire serial interface. Low current design permits operation with typical standby and active currents of only 10 µ and 1 m respectively. he device has a page write capability for up to 16 bytes of data and has fast write cycle times of only 1 m for both byte and page writes. Functional address lines allow the connection of up to eight 2402 devices on the same bus for up to 16 bits of contiguous EEROM memory. he device is available in the standard 8-pin DI, 8-pin OI (150 mil) and O packages. I/O ontrol Logic D L Vcc Vss Memory ontrol Logic XDE EEROM rray Write-rotect ircuitry YDE ense mp. R/W ontrol I 2 is a trademark of hilips orporation Microchip echnology Inc. D21202D-page 1 ELERIL HRERII bsolute Maximum Ratings ( ) V...7.0V ll inputs and outputs w.r.t. V V to V +1.0V torage temperature to +150 mbient temperature with power applied to +125 ED protection on all pins... 4 kv NOIE: tresses above those listed under bsolute Maximum Ratings may cause permanent damage to the device. his is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. BLE 1-1: D HRERII ll parameters apply across the V = +4.5V to +5.5V specified operating ranges unless ommercial (): = 0 to +70 otherwise noted. Industrial (I): = -40 to +85 utomotive (E): = -40 to +125 arameter ymbol Min. Max. Units onditions L and D pins: High-level input voltage VIH 0.7 V V Low-level input voltage VIL 0.3 V V Hysteresis of chmitt rigger inputs VHY 0.05 V V (Note) Low-level output voltage VOL 0.40 V IOL = 3.0 m, Vcc = 4.5V Input leakage current ILI ±1 µ VIN = 0.1V to 5.5V, W = Vss Output leakage current ILO ±1 µ VOU = 0.1V to 5.5V in capacitance (all inputs/outputs) IN, OU 10 pf V = 5.0V (Note) = 25, f = 1 MHz Operating current I Read 1 m V = 5.5V, L = 400 khz I Write 3 m V = 5.5V tandby current I 50 µ V = 5.5V, D = L = V W = V Note: his parameter is periodically sampled and not 100% tested. D21202D-page Microchip echnology Inc. 2402 BLE 1-2: HRERII ll parameters apply across the specified operating ranges unless otherwise noted. V = +4.5V to +5.5V ommercial (): = 0 to +70 Industrial (I): = -40 to +85 utomotive (E): = -40 to +125 arameter ymbol Min. Max. Min. Max. Units Remarks lock frequency FL khz lock high time HIGH ns lock low time LOW ns D and L rise time R ns (Note 1) D and L fall time F ns (Note 1) tart condition hold time HD: ns fter this period the first clock pulse is generated tart condition setup time U: ns Only relevant for repeated tart condition Data input hold time HD:D 0 0 ns (Note 2) Data input setup time U:D ns top condition setup time U:O ns Output valid from clock ns (Note 2) Bus free time BUF ns ime the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum Input filter spike suppression (D and L pins) OF B 250 ns (Note 1), B 100 pf ns (Note 3) Write cycle time WR ms Byte or age mode Endurance 1M 1M cycles 25, V = 5.0V, Block mode (Note 4) Note 1: Not 100% tested. B = total capacitance of one bus line in pf. 2: s a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of L to avoid unintended generation of tart or top conditions. 3: he combined and VHY specifications are due to chmitt rigger inputs which provide improved noise spike suppression. his eliminates the need for a I specification for standard operation. 4: his parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the otal Endurance Model which can be obtained from our web site. FIGURE 1-1: BU IMING D F HIGH R L U: D IN HD: LOW HD:D U:D U:O BUF D OU 2003 Microchip echnology Inc. D21202D-page 3 IN DERIION he descriptions of the pins are listed in able 2-1. BLE 2-1: IN FUNION BLE Name Function Vss Ground D erial Data L erial lock V +4.5V to 5.5V ower upply 0, 1, 2 hip elects W Hardware Write-rotect 3.0 FUNIONL DERIION he 2402 supports a bidirectional 2-wire bus and data transmission protocol. device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. he bus has to be controlled by a master device which generates the serial clock (L), controls the bus access, and generates the tart and top conditions, while the 2402 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. 2.1 D erial Data his is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the D bus requires a pull-up resistor to V (typical 10 kω for 100 khz, 2 kω for 400 khz). For normal data transfer D is allowed to change only during L low. hanges during L high are reserved for indicating the tart and top conditions. 2.2 L erial lock his input is used to synchronize the data transfer from and to the device , 1, 2 he levels on these inputs are compared with the corresponding bits in the slave address. he chip is selected if the compare is true. Up to eight 2402 devices may be connected to the same bus by using different hip elect bit combinations. hese inputs must be connected to either V or V. 2.4 W his is the hardware write-protect pin. It must be tied to V or V. If tied to Vcc, the hardware write protection is enabled. If the W pin is tied to Vss the hardware write protection is disabled. 2.5 Noise rotection he 2402 employs a V threshold detector circuit which disables the internal erase/write logic if the V is below 3.8 volts at nominal conditions. he L and D inputs have chmitt rigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. D21202D-page Microchip echnology Inc. BU HRERII he following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. hanges in the data line while the clock line is high will be interpreted as a tart or top condition. ccordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus not Busy () Both data and clock lines remain high. 4.2 tart Data ransfer (B) high-to-low transition of the D line while the clock (L) is high determines a tart condition. ll commands must be preceded by a tart condition. 4.3 top Data ransfer () low-to-high transition of the D line while the clock (L) is high determines a top condition. ll operations must be ended with a top condition. 4.4 Data Valid (D) he state of the data line represents valid data when, after a tart condition, the data line is stable for the duration of the high period of the clock signal. he data on the line must be changed during the low period of the clock signal. here is one bit of data per clock pulse. Each data transfer is initiated with a tart condition and terminated with a top condition. he number of the data bytes transferred between the tart and top conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. 4.5 cknowledge Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. he master device must generate an extra clock pulse which is associated with this cknowledge bit. Note: he 2402 does not generate any cknowledge bits if an internal programming cycle is in progress. he device that acknowledges has to pull down the D line during the cknowledge clock pulse in such a way that the D line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. master must signal an end of data to the slave by not generating an cknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the top condition (Figure 4-2). FIGURE 4-1: L D RNFER EQUENE ON HE ERIL BU HRERII () (B) () (D) () () D tart ondition ddress or cknowledge Valid Data llowed to hange top ondition FIGURE 4-2: NOWLEDGE IMING cknowledge Bit L D Data from transmitter Data from transmitter ransmitter must release the D line at this point allowing the Receiver to pull the D line low to acknowledge the previous eight bits of data. Receiver must release the D line at this point so the ransmitter can continue sending data Microchip echnology Inc. D21202D-page 5 DEVIE DDREING control byte is the first byte received following the tart condition from the master device (Figure 5-1). he control byte consists of a four bit control code; for the 2402 this is set as 1010 binary for read and write operations. he next three bits of the control byte are the hip elect bits (2, 1, 0). he hip elect bits allow the use of up to eight 2402 devices on the same bus and are used to select which device is accessed. he hip elect bits in the control byte must correspond to the logic levels on the corresponding 2, 1, and 0 pins for the device to respond. hese bits are in effect the three Most ignificant bits of the word address. he last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. Following the tart condition, the 2402 monitors the D bus checking the control byte being transmitted. Upon receiving a 1010 code and appropriate hip elect bits, the slave device outputs an cknowledge signal on the D line. Depending on the state of the R/W bit, the 2402 will select a read or write operation. FIGURE 5-1: tart Bit ontrol ode ONROL BYE FORM R/W lave ddress Read/Write Bit hip elect Bits cknowledge Bit 5.1 ontiguous ddressing cross Multiple Devices he hip elect bits 2, 1, 0 can be used to expand the contiguous address space for up to 16 bits by adding up to eight 2402 devices on the same bus. In this case, software can use 0 of the control byte as address bit 8, 1 as address bit 9, and 2 as address bit 10. It is not possible to write or read across device boundaries. D21202D-page Microchip echnology Inc. WRIE OERION 6.1 Byte Write Following the tart signal from the master, the device code(4 bits), the hip elect bits (3 bits) and the R/W bit which is a logic low is placed onto the bus by the master transmitter. he device will acknowledge this control byte during the ninth clock pulse. he next byte transmitted by the master is the word address and will be written into the address pointer of the fter receiving another cknowledge signal from the 2402 the master device will transmit the data word to be written into the addressed memory location. he 2402 acknowledges again and the master generates a top condition. his initiates the internal write cycle, and during this time the 2402 will not generate cknowledge signals (Figure 6-1). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command but no data will be written. he write cycle time must be observed even if the write protection is enabled. 6.2 age Write he write control byte, word address and the first data byte are transmitted to the 2402 in the same way as in a byte write. But instead of generating a top condition, the master transmits up to 15 additional data bytes to the 2402 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a top condition. fter the receipt of each word, the four lower order address pointer bits are internally incremented by one. he higher order four bits of the word address remains constant. If the master should transmit more than 16 bytes prior to generating the top condition, the address counter will roll over and the previously received data will be overwritten. s with the byte write operation, once the top condition is received an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command but no data will be written. he write cycle time must be observed even if the write protection is enabled. Note: age write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. hysical page boundaries start at addresses that are integer multiples of the page buffer size (or page size ) and end at addresses that are integer multiples of [page size - 1]. If a age Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. 6.3 WRIE ROEION he W pin must be tied to V or V. If tied to V, the upper half of the array (080-0FF) will be writeprotected. If the W pin is tied to V, then write operations to all address locations are allowed. FIGURE 6-1: Bus ctivity Master D Line R BYE WRIE ontrol Byte Word ddress Data O Bus ctivity FIGURE 6-2: Bus ctivity Master R GE WRIE ontrol Byte Word ddress (n) Data n Data n +1 Data n + 15 O D Line Bus ctivity 2003 Microchip echnology Inc. D21202D-page 7 NOWLEDGE OLLING ince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the top condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. polling can be initiated immediately. his involves the master sending a tart condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no will be returned. If no is returned, then the tart bit and control byte must be re-sent. If the cycle is complete, then the device will return the and the master can then proceed with the next Read or Write command. ee Figure 7-1 for flow diagram. FIGURE 7-1: NOWLEDGE OLLING FLOW end Write ommand end top ondition to Initiate Write ycle end tart end ontrol Byte with R/W = RED OERION Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. here are three basic types of read operations: current address read, random read, and sequential read. 8.1 urrent ddress Read he 2402 contains an address counter that maintains the address of the last word accessed, internally incremented by one. herefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the 2402 issues an acknowledge and transmits the eight bit data word. he master will not acknowledge the transfer but does generate a top condition and the 2402 discontinues transmission (Figure 8-1). 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. o perform this type of read operation, first the word address must be set. his is done by sending the word address to the 2402 as part of a write operation. fter the word address is sent, the master generates a tart condition following the acknowledge. his terminates the write operation, but not before the internal address pointer is set. hen the master issues the control byte again but with the R/W bit set to a one. he 2402 will then issue an acknowledge and transmits the eight bit data word. he master will not acknowledge the transfer but does generate a top condition and the 2402 discontinues transmission (Figure 8-2). fter this command, the internal address counter will point to the address location following the one that was just read. Did Device cknowledge ( = 0)? YE Next Operation NO 8.3 equential Read equential reads are initiated in the same way as a random read except that after the 2402 transmits the first data byte, the master issues an acknowledge as opposed to a top condition in a random read. his directs the 2402 to transmit the next sequentially addressed 8-bit word (Figure 8-3). o provide sequential reads the 2402 contains an internal address pointer which is incremented by one at the completion of each operation. his address pointer allows the entire memory contents to be serially read during one operation. he internal address pointer will automatically roll over from address FF to address 00. D21202D-page Microchip echnology Inc. 2402 FIGURE 8-1: URREN DDRE RED Bus ctivity Master D line R ontrol Byte Data O Bus ctivity N O FIGURE 8-2: RNDOM RED Bus ctivity Master R ontrol Byte Word ddress (n) R ontrol Byte Data (n) O D line Bus ctivity N O FIGURE 8-3: Bus ctivity Master D line Bus ctivity EQUENIL RED ontrol Byte Data n Data n + 1 Data n + 2 Data n + X N O O 2003 Microchip echnology Inc. D21202D-page 9 2402 ENDIX : REVIION HIORY Revision D orrections to ection 1.0, Electrical haracteristics. D21202D-page Microchip echnology Inc. 2402 ON-LINE UOR Microchip provides on-line support on the Microchip World Wide Web site. he web site is used by Microchip as a means to make files and information easily available to customers. o view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Internet Explorer. Files are also available for F download from our F site. onnecting to the Microchip Internet Web ite he Microchip web site is available at the following URL: he file transfer site is available by using an F service to connect to: ftp://ftp.microchip.com he web site and file transfer site provide a variety of services. Users may download files for the latest Development ools, Data heets, pplication Notes, User's Guides, rticles and ample rograms. variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: Latest Microchip ress Releases echnical upport ection with Frequently sked Questions Design ips Device Errata Job ostings Microchip onsultant rogram Member Listing Links to other useful web sites related to Microchip roducts onferences for products, Development ystems, technical information and more Listing of seminars and events YEM INFORMION ND UGRDE HO LINE he ystems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. l
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