1st IEEE Inernaional Conference on Power Elecronic, Inelligen Conrol and Energy Syem (ICPEICES2016)
A Seven Level Multilevel Inverter Topology with Improved Results using PWM Technique
Vy Go, Jgds Kumr2 d Jm Gmbr3
1,2,3Depaent ofElectrical Engg. PEC University ofTechnology Chandigah India
Absaet
The new emerging multi level inverer topologies with reduced device count, beter control strategies improved modulation schemes and capability to address various operational issues have proved to be highly superior to that of two level inverers and the conventional multilevel inverter topologies. This paper presents signicantly improved results of an existing
6
sitches and
DC sources multilevel inverer topology to produce great perfection in the seven level output voltage waveform. The major impact of the improved results is the reduction in total harmoni distortion (THD). The control methodology employed is Level Shied PWM technique based on which the topology is simulated for Phase Opposition Disposition Alternate Phase Opposition Disposition and Alternate Phase Opposition Disposition
+
Variable Frequency modulation techniques. Multilevel Inverters today present a viable solution for high dynami performance and power quality seeking appliations ultimately focusing to achieve almost perfect sinusoidal output voltage with minimum harmoni content. Thus in this paper an effort is made to reduce the THD in the output voltage waveform. An analysis is done and a comparison is also made between the existing results and the new results obtained. These results are veried using MATLAB/SIMULINK and the analysis of harmoni spectrum is done through the Fast Fourier transform window.
KywordsMultlvl Invrt;
N
Topologis; Total Harmonie Distoron; Ll Shtd Mulearrir
PW
Tehniqus
I.
NTRODTION
The Conventional cascaded seven level m ulti level nverters utilize tree DC sources and twelve switches [][6]. Many compaisons have been made by various authors between the diode camped ying capacitor and the cascaded Hbridge MLI [7][8]. The man disadvantage n these structes is that for higher levels of the output voltage higher number of power switches is requred. Hence improvement is requred to lower the no. of switches of the inverter. This topology utilizes four DC sources and six switches and it produces the output voltage waveform with signicantly less harmonics as compared to conventional cascaded multilevel inverter [9]. The ndamental concept of an MLI to generate nea to sinusoidal output voltage waveform is by using power electronic switches like IGBTs MOSFETs etc. along with appropriate DC voltage sour ces to perform the power conversion i.e. the DC to AC conversion. Capacitors batteries and renewable energy voltage soces can be used as the multiple nput DC sources. Snce the batteries
9781467385879/16/$31.00 ©2016 IEEE
[1)
must be isolated om the semiconductor switches and the other Hbridges hence a sepate maxmm power point ackng (MPPT) chage conoller is requred to chage its storage batteries ndependently. Hence a PV system that uses the cascaded Hbridge multilevel inverter topology can be quite bulk and costly. Moreover due to the ntermitent nate ofthe renewable energy sources the performance and eciency ofthe mutilevel inverter may deteriorate. For this the output voltage quality ofthe MLI is mproved as the number of output voltage level ncrease reachng to that ofthe perfect sinusoid. Also the quantity and size of output lters can be reduced because of the reduction n the lower order hamonics content in the output votage waveform.
O
the other hand with lesser number of levels they need lage sized as wel as expensive LC output lters. A multilevel inverter offers various advantages over a conventional two level inverter by employing a high switchng equency PM which not only produces the output votage with lower hamonic distortion but also reduces dv/dt sesses thereby reducng elecomagnetic compatibility (EMC) problems these advantages will be elaborated later in this paper. Since hamonics play a major role n context of power electronics ther reduction is the primary motive in this paper so that the multilevel inverter topology can be applied to various high power quality seeking applications. To be knon as a multilevel inverter each phase ofthe inverter should produce at least tree dierent voltages and this dierentiates the conventional twoevel voltage source nverter (LVSI) om the multilevel family. In this paper the crcuit is checked out using level shied multicarier PWM teciques [0]. Then identiing the effectiveness by workng the simulated circuit with InPhase Disposition (PD) Phase Opposition Disposition (POD) Alteate Phase Opposition Disposition (APOD) PM modulation schemes [][] usng
M
TLAB/SIMLINK.
OPOLOGIES
A
Canventianl Tapa/a
Cascaded HBridge multilevel inverters ae obtaned by connectng n series more than two single phase HBridge nverters each consistng of 4 switches hence the name [][4]. In general terms when conectng k HBridges n series k+ dierent voltage levels are obtaned and maxim output voltage kVã Thus for a seven level inverter it uses HBridges n series hence a
1st IEEE Inernaional Conference on Power Elecronic, Inelligen Conrol and Energy Syem (ICPEICES2016)
total of switches and maxmum output votage ofVdc. It is important to note that the two switches connected n the same leg must not conduct at the same tme n order to prevent a complete short crcuit. Fig. represents the Conventional Cascaded H bridge nverter.
Vdel VdeZ
V
d
c
Fig.
I:
ascaded H bridge Structure for Seven evel MultilevelInverter
B
Level 6 Switch Tapala
This topology uses 4 dc votage sour ces and 6 switches as shon in Fig. . Switches S S S are utilized for producng levels while switches S4 S5 ae utilized for reversing the polarity [5]. The switch S6 is connected across the load for obtanng zero level. Table represents its switchng sequence. In this topology the nber of switches and percentage of T produced is much lesser as compaed to the conventional and other existng 9 switch 7 switch topologies. switches conduct n the positive half cycle and two switches conduct for the negative half cycle and one switch for generatng zero level. Here level shing PWM tecnique is used.
Fig. 2: Seven Level
6
Switch MultilevelInverter Topology
[
T ABLE
I:
WICHING AES OF 6WICH
4
OURCE TOPOLOGY
Sr. No. S] S2 S3 S S S6 Vo 1 0 0 I 0 I 0
Vdc 2.
0 I 0 0 I 0
2Vdc
3.
I 0 0 0 I 0
3Vdc
4 0 0 0 0 0 I 0 5 I 0 0 I 0 0
 Vdc
6.
0 I 0 I 0 0
 2Vdc 7.
0 0 I I 0 0
 3Vdc Where, refers to OFF;
I
refers to ON.
III.
ETHOOLOGY SE
In ode o ealie he muilevel invee opology a paticula conol sategy needs to be used. There are many controllng schemes n literate; one ofthese is the modulation tecnique that can be cassied based on the switchng equency. These include: ndamental switchng equency where each nverter n one cycle undergoes one commutation e.g. Selective Harmonic Elmnation (S) Space Vector Conol (SVC) and Nearest Votage Level Conol (NVLC) and high switchng equency modulation tecnique where n one cycle the nverter dergoes several commutations e.g. PM tecnique and Space Vector Modulation (SVM). One of the simplest methods of obtanng votage source modulation is tough intersectng a modulatng signal which is mostly a sne wave with i angular carrier waveform. This scheme is explaned as n carrier based PM technique [6]. Muticarrier P Tecniques can be categorized in two groups i.e.; Level Shied methods (LS) and Phase Shied (PS) P methods [7] latter produces higher amot of total harmonic distortion as compared to former. Therefore Level Shied P tecnique is considered [8]. Level shing tecnique is rther categorized nto tree techniques which are: InPhase Disposition (PD) Phase Opposition Disposition (POD) and Alteate Phase Opposition Disposition (APOD) [9][0]. hen usng level shied P tecnique an 'N level inverter uses 'N carrier waves such that the 'N iangular caiers ae vertically displaced and the bands they occupy are equally spaced. Moreover along with the vertical displacement there is also phase reversal between the i angula cariers. InPhase Disposition (PD) nvolves all the carriers n phase [] which when compaed with the sinusoidal reference produce the desred pulses. Appropriate comparisons ae made and accordng to the desired pulse pate the logical crcuits are used. The pulses thus obtaned ae fed to the power electronic switch n this case MOSFET and the desred seven level output votage waveform is obtained. In this paper for e.g. n order to obtan V votage level switches S and S5 should be ON thus we now know the desired pulse patte. To achieve this patte comparisons ae made between the snusoidal reference and the iangula cariers and if desired additional logical circuits can be used.
1st IEEE Inernaional Conference on Power Elecronic, Inelligen Conrol and Energy Syem (ICPEICES2016)
Here the same topology is simulated for POD APOD and APOD+VF modulation tecnique and the desred seven level output votage waveform is obtaned. In the case of Phase Opposition Disposition (POD) [] as shon in Fig. all the iangular carriers above zero reference are n same phase whereas those below zero reference ae 80 degrees out ofphase.
1 I I
�
C E
'
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
tm
Fig. 3: POD PWM Technique
Each carier is 80 degrees in phase dierence with its neighborng carier n Alteate Phase Opposition Disposition (APOD) as shon n Fig. 4.
I
C E
'
1
Fig.
4:
APOD PWM Technique
In APOD+VF tecnique each carier wave is displaced to its adjacent carrier wave by 80 degrees [][4] such that the carrier equency ofthe lower most and the uppermost carier waves is appropriately increased as shon n Fig. 5.
[
�
C E
'
0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
tm
Fig.
5:
APOD+VF PWM Technique
IV.
IMULATION SULTS
The above discussed 7 level 6 switch topology is simulated based on the POD APOD APOD+VF P tecnique and the hamoni spectr is analyzed using MTLAB/ Simulnk. The aplitude of the dc source is taken as V and load resistance is 0 oms. MOSFET block paraeters are as folows: FET resistance= .ohms Inteal Diode Resistance =kilo oms The resuts we obtained ae shon n Fig. 6 Fig. 7 and Fig. 8.
Selected
ig
na
l:
y les.
w
indo
(in red):
cles
:
r
l
002
004
005 008 0
T \
T
analysis

r c
C
E
r
c

>
'
r
Fundam en tal
5 Hz
=
27
ã
THD=
577 %
00 0 50
40
20 0
_
.
.
J
0 00
400
500 00
Fequenc Hz)
Fig. 6: FFT Analysis of7 Level 6Switch Topology using POD PWM Technique
000
1st IEEE Inernaional Conference on Power Elecronic, Inelligen Conrol and Energy Syem (ICPEICES2016)
Selected signal:
5
y les. FF wndo w (in red) 3 yles
:
r
\
7
1
o
00 00 4 006 00 01
(
T
analysis

Fundamental
0Hz)
=
28
,
HD=
146
%
100
C
80
E
60
§
L
40
�
'
0
:
J
_
.
.
_I
00
00
600 800 1000
Frequency (Hz)
Fig. 7: FFT Analysis of7 Leve6Switch Topology using APOD PWM Technique
Selected signal
5
y es FF win o w (in red)
3
y les
J
\
\17
o
002
0.04
006 008 01
T (
T
analysis
undamenal
0Hz)
3046
, TD
10.35
00
�
0
�
60
§

40
'
0
�
I .
200
400
600 00 1000 Frequeny (Hz)
Fig. 8: FFT Analysis of7 Leve6Switch Topology using APOD+VF PWM Technique
V.
COMPSON OF SUL TS T
ABLE
2:
OMPARISON OF
THD
OF EVEN EVEL IX WICH TOPOLOGY BEWEEN XISlNG SULS AND ROPOSED SULS
Sr. Topology Existing Proposed No. Results% Results% THD 2 THD I
Seven level six switch topology 18.25% 16.77% with 4 D
source using Phase Opposition Disposition PWM technique 2. Seven level six switch topology 16.48% 14.61% with 4 D
source using lternate Phase Opposition Disposition PWM technique
3.
Seven level six switch topology 10.35% with 4 D
source using lternate Phase Opposition Disposition + Variable Frequency PWM technique
[4
Based on the above simulation results it can be seen that the percentage T obtaned n the sevenevel multilevel nverter topology is lesser than that of the results given n the reference [5]. A detailed compaison is made based on the above T analysis for POD APOD and APOD+VF modulation tecnique as shon n Table . A comparison of the T of the obtaned results and various other existng multilevel inverter topologies are shon n Table .
TABLE
3:
ERCENAGE
THD
OMPARISON OF IFFEEN TOPOLOGIES
PWM Technique PD POD APOD APOD+VF
ascaded 7  level 24.26 23.13 22.46 7 level 9 switch  20.52 7 level 7 switch symmetrical 18.15 7 level 7 switch asymmetrical 15.79 7 level 6 switch 4 dc source 16.77 14.76 10.35 7 level 6 switch 3 dc source 15.91 7 level 6 switch asymmetrical 18.69 
Thus it can be seen om Table that the proposed results ae better than the existng results such that for Phase Opposition Disposition P tecnique the percentage T in the existng results is 8.5% and that n the proposed results is 6.77% for Alteate Phase Opposition Disposition P tecnique the percentage T in the existng results is 6.48% and that in the proposed results is 4.6%. Hence the proposed results ae signicantly better than the existng results. Moreover n the reference [5] the topology is not simulated for Alteate Phase Opposition Disposition + Variable Frequency P tecnique but n this paper the topology is simulated for this P technique and the percentage T thus obtaned is 0.5%. Hence it is worth mentionng that the percentage T is mnimum for Alteate Phase Opposition Disposition + Variable Frequency P technique which n the case of multilevel nverters is a signicantly good result. The multilevel approach for DC to AC conversion offers many advantages such as:
ã
The starcase waveform not only ehibits an improved hamoni prole but also the dv/dt stresses are greatly reduced. Thus mnmizng the lter size or even elimnatng lter requrement and at the sae tme electromagnetic compatibility problems can be adessed.
ã
MLI produces much lesser sess n the bearng of a motor because the common mode voltage produced is much smaller when the motor is used n a multilevel motor ive application
ã
Renewable energy sources such as sola PV cells wind energy and el cells can be readily ncorporated n the multilevel converter tecnology and the nput sources can be controlled for equal load shang.