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VERY IMPORTANTNOTES Out of various techniques to minimize the leakage and sub-threshold currents to minimize static power dissipation one can use a variable threshold CMOS (VTCMOS) circuit, which is easier to achieve and is further discussed here. The basic principle of a VTMOS circuit is to keep the substrate separate from source and apply different voltage to it with respect to source (See Figure-2). Figure 2. A variable threshold CMOS inverter H
   VERY IMPORTANTNOTES Out of various techniques to minimize the leakae an! su #threshol! currents to minimize static $o%er !issi$ation one can use a varia le threshol! &MOS 'VT&MOS( circuit) %hich is easier to achieve an! is further !iscusse! here* The asic $rinci$le of a VTMOS circuit is to kee$ the su strate se$arate from source an! a$$l+ !ifferent voltae to it %ith res$ect to source'See ,iure#-(*  Figure 2. A variable threshold CMOS inverter  .ere the su strates of $MOS an! nMOS transistors are se$arate! out an! have their o%n voltae source) %hich is calle! su strate ias control circuit* The threshol! voltae Vt of the MOS !evice is a function of its source#to#su strate voltae Vs * Normall+ the su strate of an nMOS transistor is connecte! to /N0 an! the su strate of $MOS transistor is connecte! to V00* This ensures the reverse ias con!ition of source an! !rain %ith res$ect to su strate* There is a !e$letion reion aroun! source an! !rain %hich inhi its the con!uction throuh su strate* Onl+ the leakae current can flo% et%een source#su strate an! !rain#su strate* .o%ever) if the !e$letion reion et%een source#su strate an! !rain#su strate is increase!) the leakae current can e further minimize!) %hich is the role of the VT&MOS circuit* 0urin active o$eration the voltae of nMOS su strate is ke$t at 1V 'on /N0 at %hich the source is also ke$t( an! the voltae of $MOS su strate is ke$t at -V 'equal to source voltae(*2hen the circuit is in stan! + mo!e) as !e$icte! in ,iure -) the su strate voltaes are chane! throuh a su strate ias control circuit* It is 3V for $MOS an! #-V for nMOS) minimizin the static $o%er !issi$ation + %i!enin the !e$letion reion an! re!ucin the leakae currents* A !ra% ack of this metho! is that it requires an e4tra voltae source for su strate iasin an! su strate ias control circuitr+ that results in increasin the chi$ area*
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