ADuCM320 Hardware Reference Manual UG PDF

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UG-498 One Technology Way P.O. Box 9106 Norwood, MA , U.S.A. Tel: Fax: How to Set Up and Use the ADuCM320 SCOPE This reference manual provides a detailed
UG-498 One Technology Way P.O. Box 9106 Norwood, MA , U.S.A. Tel: Fax: How to Set Up and Use the ADuCM320 SCOPE This reference manual provides a detailed description of the ADuCM320 functionality and features. DISCLAIMER Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. FUNCTIONAL BLOCK DIAGRAM BUF_VREF2V5 XTALO XTALI ECLKIN AIN0 AIN5 AIN6 MUX 2.5V BAND GAP 14-BIT SAR ADC 1.8 V LDO CLOCK SYSTEM kHz 16MHz OSC 80MHz PLL DGNDx AVDDx AGNDx IOVDDx IOGNDx AIN15 VDAC0 VDAC INTERNAL CHANNELS: TEMPERATURE, AV DD, IOV DD COMPARATOR ARM CORTEX-M3 PROCESSOR MEMORY 2 128kB FLASH 32kB SRAM GPIO PORTS UART 2 SPI 2 I 2 C EXT IRQs MDIO PLA GENERAL PURPOSE I/O PORTS VDAC7 IDAC0 VDAC IDAC ADuCM320 DMA NVIC 3 GENERAL PURPOSE TIMER WATCHDOG TIMER WAKE-UP TIMER PWM PWM0 TO PWM6 IDAC3 IDAC RESET SYSTEM SERIAL WIRE SWDIO SWCLK PVDDx PGND RESET Figure PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. C Page 1 of 196 UG-498 TABLE OF CONTENTS Scope... 1 Disclaimer... 1 Functional Block Diagram... 1 Revision History... 4 Using the... 6 Number Notations... 6 Register Access Conventions... 6 Acronyms and Abbreviations... 6 Introduction to the ADuCM Main Features of ADuCM Memory Organization... 8 Clocking Architecture Clocking Architecture Features Clocking Architecture Block Diagram Clocking Architecture Overview Register Summary: Clock Architecture Clocking Architecture Operation Register Details: Clock Architecture Power Management Unit Power Management Unit Features Power Management Unit Overview Power Management Unit Operation Code Examples Register Summary: Power Management Unit Register Details: Power Management Unit ARM Cortex-M3 Processor ARM Cortex-M3 Processor Features ARM Cortex-M3 Processor Overview ARM Cortex-M3 Processor Operation ARM Cortex-M3 Processor Related Documents ADC Circuit ADC Circuit Features ADC Circuit Block Diagram ADC Circuit Overview ADC Circuit Operation ADC Transfer Function ADC Typical Setup Sequence ADC Input Buffer ADC Internal Channels ADC Support Circuits Register Summary: ADC Circuit Register Details: ADC Circuit Register Summary: Additional Registers Register Details: Additional Registers Analog Comparator Analog Comparator Features Analog Comparator Overview Analog Comparator Operation Register Summary: Analog Comparator Register Details: Analog Comparator IDACs IDAC Features IDAC Block Diagram IDAC Overview Register Summary: IDAC Register Details: IDAC VDACs VDAC Features VDAC Block Diagram VDAC Overview VDAC Operation Register Summary: VDAC Register Details: VDAC System Exceptions and Peripheral Interrupts Cortex-M3 and Fault Management External Interrupt Configuration Register Summary: External Interrupts Register Details: External Interrupts Low Voltage Analog Die Interrupt Configuration Register Summary: Low Voltage Die Interrupts Register Details: Low Voltage Die Interrupts Reset Reset Features Reset Operation Register Summary: Reset Register Details: Reset DMA Controller DMA Features DMA Overview DMA Operation Rev. C Page 2 of 196 DMA Interrupts DMA Priority Channel Control Data Structure Control Data Configuration DMA Transfer Types (CHNL_CFG[2:0]) Address Calculation Aborting DMA Transfers Register Summary: DMA Register Details: DMA Flash Controller Flash Controller Features Flash Controller Overview Flash Controller Operation Flash Memory Operation Flash Protection Register Summary: Flash Controller Register Details: Flash Controller Silicon Identification Silicon Identification Memory Mapped Registers Digital Die ID Register Low Voltage Die ID Register Digital I/Os Digital I/Os Features Digital I/Os Block Diagram Digital I/Os Overview Digital I/Os Operation Digital Port Multiplex Register Summary: Digital I/O Register Details: Digital I/O I 2 C Serial Interface I 2 C Features I 2 C Overview I 2 C Operation I 2 C Operating Modes Register Summary: I2C Register Details: I2C Register Summary: I2C Register Details: I2C Serial Peripheral Interfaces SPI Features SPI Overview UG-498 SPI Operation SPI Transfer Initiation SPI Interrupts SPI Wire-OR ed Mode (WOM) SPI CSERR Condition SPI DMA SPI and Power-Down Modes Register Summary: SPI Register Details: SPI Register Summary: SPI Register Details: SPI UART Serial Interface UART Features UART Overview UART Operation Register Summary: UART Register Details: UART PLA PLA Features PLA Overview PLA Operation Register Summary: PLA Register Details: PLA General-Purpose Timers General-Purpose Timers Features General-Purpose Timers Block Diagram General-Purpose Timers Overview General-Purpose Timers Operation Register Summary: General-Purpose Timer Register Details: General-Purpose Timer Register Summary: General-Purpose Timer Register Details: General-Purpose Timer Register Summary: General-Purpose Timer Register Details: General-Purpose Timer Watchdog Timer Watchdog Timer Features Watchdog Timer Block Diagram Watchdog Timer Overview Watchdog Timer Operation Register Summary: Watchdog Timer Register Details: Watchdog Timer Rev. C Page 3 of 196 UG-498 Wake-Up Timer Wake-Up Timer Features Wake-Up Timer Block Diagram Wake-Up Timer Overview Wake-Up Timer Operation Register Summary: Wake-Up Timer Register Details: Wake-Up Timer PWM PWM Features PWM Overview PWM Operation PWM Interrupt Generation Register Summary: PWM Register Details: PWM MDIO MDIO Features MDIO Overview MDIO Operation Block Switching Register Summary: MDIO Interface (MDIO) Register Details: MDIO Hardware Design Considerations Typical System Configuration Serial Wire Debug Interface REVISION HISTORY 1/2017 Rev. B to Rev. C Changes to Clocking Architecture Operation Section Changes to ADC Circuit Features Section Changes to ADC Circuit Overview Section Changes to Single-Ended Mode Section and Differential Section Changes to ADC Voltage Reference Selection Section Changes to Table Added IDAC Thermal Shutdown Section Changes to Writing to Flash Section Changes to Table Changes to Table /2016 Rev. A to Rev. B Changes to Table Changes to Table Changes to Protection, Integrity Section Added ECC Error Handling Section, ECC Error During Read Section, and ECC Error During Execution of Sign Command Section Changes to Table 95 and Table Added ECC Enable/Disable, Error Response Register Section, Flash 0 ECC Error Address Register Section, Flash 1 ECC Error Address Register Section, and Table 112 to Table 114; Renumbered Sequentially Added MDIO Interrupt Power-Up Register Write Sequence Section /2015 Rev. 0 to Rev. A Changes to Figure Changes to Register Access Conventions Section... 6 Changes to Introduction to the ADuCM320 Section... 7 Moved Register Summary: Clock Architecture Section Changes to Table 4 and Clocking Architecture Operation Section Rev. C Page 4 of 196 Change to Table Changes to Table 6 and Table Added Clocking Status Register Section and Table 8; Renumbered Sequentially Changes to Debug Support Section Changes to ADC Voltage Reference Selection Section Added Figure 8; Renumbered Sequentially Change to Table Changes to Table Changes to Table Changes to Table Changes to Table Changes to Case 2 Turn On IDAC2 but to Set the Output to 0 ma with the Lowest Possible Offset Section Changes to Table Changes to Table Changes to Table Added Aborting DMA Transfers Section Changed Top of Flash Blocks Section to Reserved Flash Locations Section Changes to Erasing Flash Section and Signature Section Changes to CPU Execution Speed Section Changes to Memory Cache Section Changes to Table 95 and Table Changes to Cache Status Register Section Added Table Changes to Cache Setup Register Section and Cache Key Register Section Added Table 113 and Table Deleted Shared MDIO Pins Section Changes to Digital I/Os Features Section and Digital I/Os Overview Section Added Inaccessible Bits Section Changes to I/O Pull-Up Enable (GPxPUL) Section Changes to Open-Drain Enable (GPxODE) Section... 88 Changes to Table Changes to Register Details: Digital I/O Section, GPIO Port Configuration Registers Section, GPIO Port Output Enable Registers Section, Table 120, and Table Added GPIO Port Pull-Down Enable Registers Section and Table Changes to GPIO Port Pull-Up Enable Registers Section, GPIO Port Input Path Enable Registers Section, GPIO Port Registered Data Input Registers Section, Table 122, Table 124, and Table Deleted GPIO Port 4 Configuration Register Section, GPIO Port 4 Output Enable Register Section, GPIO Port 4 Pull-Down Enable Register Section, GPIO Port 4 Input Path Enable Register Section, GPIO Port 4 Registered Data Input Section, and Table 126 to Table Deleted GPIO Port 4 Data Output Register Section, GPIO Port 4 Data Out Set Register Section, GPIO Port 4 Data Out Clear Register Section, GPIO Port 4 Pin Toggle Register Section, GPIO Port 4 Open Drain Enable Register Section, and Table 131 to Table Deleted GPIO Port 5 Configuration Register Section, GPIO Port 5 Output Enable Register Section, GPIO Port 5 Pull-Down Enable Register Section, GPIO Port 5 Input Path Enable Register Section, d3fgpio Port 5 Registered Data Input Section, and Table 136 to Table Deleted GPIO Port 5 Data Output Register Section, GPIO Port 5 Data Out Set Register Section, GPIO Port 5 Data Out Clear Register Section, GPIO Port 5 Pin Toggle Register Section, UG-498 GPIO Port 5 Open Drain Enable Register Section, and Table 141 to Table Changes to GPIO Port Data Output Registers Section, GPIO Port Data Out Set Registers, GPIO Port Data Out Clear Registers, Table 126, Table 127, and Table Changes to GPIO Port Pin Toggle Registers Section, GPIO Port Open-Drain Enable Registers, Table 129, and Table Changes to I 2 C Features Section Added I 2 C Slave Mode Late Loading of I2CSTX Issue Section Changes to Table Changes to Table Changes to Table Changes to Table Changes to Table Changes to Table Changes to PWM Overview Section and PWM Operation Section Changes to Figure Changes to Table Changes to H-Bridge Mode, Table 264, and PWM Interrupt Generation Section Changes to Table Change to Figure Changes to Table Changes to Figure Changes to Table 294 and Table /2014 Revision 0: Initial Version Rev. C Page 5 of 196 UG-498 USING THE ADuCM320 HARDWARE REFERENCE MANUAL NUMBER NOTATIONS Table 1. Number Notations Notation Description Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0. V[x:y] Bit field representation covering Bit x to Bit y of a value or a field (V). 0xNN Hexadecimal (Base 16) numbers are preceded by the prefix 0x. 0bNN Binary (Base 2) numbers are preceded by the prefix 0b. NN Decimal (Base 10) numbers are represented using no additional prefixes or suffixes. REGISTER ACCESS CONVENTIONS Table 2. Register Access Conventions Mode Description Memory location has read and write access. RC Memory location is cleared after reading it. R Memory location is read access only. A read always returns 0, unless otherwise specified. W Memory location is write access only. MMR bits that are not documented are reserved. When writing to MMRs with reserved bits, the reserved bits should be written with the value in the reset column of the relevant MMR description, unless otherwise noted. ACRONYMS AND ABBREVIATIONS Table 3. Acronyms and Abbreviations Acronym/Abbreviation Description ADC Analog-to-digital converter DMA Direct memory access DDM Digital diagnostic monitoring GPIO General-purpose input and output LSB Least significant byte/bit MDC Management data input/output clock MDIO Management data input/output MMD MDIO manageable device (slave) MMR Memory mapped register MSB Most significant byte/bit NMI Nonmaskable interrupt NVIC Nested vectored interrupt controller NVR Nonvolatile registers Rx Receive SAR Successive approximation register SOA Semiconductor optical amplifier SPI Serial peripheral interface STA Station management entity (host/master) SWD Sync word detect/serial wire debug Tx Transmit UART Universal asynchronous transmitter VR Volatile registers WDT Watchdog timer WUT Wake-up timer Rev. C Page 6 of 196 UG-498 INTRODUCTION TO THE ADuCM320 The ADuCM320 is a fully integrated single-package device that incorporates high performance analog peripherals together with digital peripherals controlled by an 80 MHz ARM Cortex -M3 processor and integral flash for code and data. The ADC on the ADuCM320 provides 14-bit, 1 MSPS data acquisition on up to 16 input pins that can be programmed to be single-ended or differential. Additionally, chip temperature and supply voltages can be measured. The ADC input voltage is 0 V to VREF. A sequencer is provided that allows a user selected set of ADC channels to be measured in sequence without software involvement during the sequence. The sequence can optionally auto repeat at a user-selectable rate. Up to eight voltage DACs are provided with output ranges programmable to one of two voltage ranges. The DAC outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. On the ADuCM320, four current output DAC sources are provided. The output currents are programmable with ranges of 0 ma to 150 ma. A low drift band gap reference and a voltage comparator complete the analog input peripheral set. The microcontroller core is a low power ARM Cortex-M3 processor, a 32-bit RISC machine that offers up to 100 MIPS peak performance. Also integrated on chip are two 128 kb Flash/EE memory and 32 kb of SRAM. The flash comprises two separate 128 kb blocks supporting execution from one flash block and simultaneous writing/erasing of the other flash block. The ADuCM320 operates from an on-chip oscillator or a 16 MHz external crystal and a PLL at 80 MHz. This clock can optionally be divided down to reduce current consumption. Additional low power modes can be set via software. In the normal operating mode, the ADuCM320 digital core consumes about 300 µa/mhz. The device includes an MDIO interface capable of operating at up to 4 MHz. The capability to simultaneously execute from one flash block and write/erase the other flash block makes the ADuCM320 ideal for 40 G/100 G optical applications. User programming is eased by receiving interrupts after PHYADR, DEVADD, and end of frame and by having PHYADR and DEVADD hardware comparators. In addition, the nonerasable kernel code plus flags in user flash can provide assistance to allow user code to robustly switch between the two blocks of user flash code and data spaces as required for MDIO. The ADuCM320 also integrates a range of on-chip peripherals that can be configured via software control as required in the application. These peripherals include one UART, two I 2 Cs, two SPI serial I/O communication controllers, GPIO, 32-element programmable logic array, three general-purpose timers, one wake-up timer, and one system watchdog timer. In addition, 16-bit PWMs with seven output signals are provided. GPIO pins on the device power up in input mode. In output mode, the software can choose between open-drain mode and push-pull mode. The outputs can drive at least 4 ma. The pull-ups can be disabled and enabled in software. In GPIO mode, the inputs can always be enabled to monitor the pins. The GPIO pins can also be programmed to handle digital or analog peripheral signals, in which case the pin characteristics are matched to the specific requirement. A large support ecosystem is available for the ARM Cortex-M3 processor, which eases product development of the ADuCM320. Access is via the JTAG serial wire interface. On-chip factory firmware supports in-circuit serial download via MDIO. These features are incorporated in a low cost QuickStart development system supporting this precision analog microcontroller family. MAIN FEATURES OF ADuCM320 ADC Multichannel, 14-bit, 1 MSPS SAR ADC Low drift on-chip voltage reference DACs Eight voltage output DACs o VDACs are 12-bit monotonic Four current output DACs o Current DACs are 12-bit monotonic Low drift, on-chip 2.5 V voltage reference source o Two buffered reference outputs Rev. C Page 7 of 196 UG-498 Communication UART o Industry standard, UART peripheral o Support for DMA Two I 2 Cs o 2-byte transmit and receive FIFOs for the master and slave o Support for DMA Two SPIs o Master or slave mode with separate 4-byte Rx and Tx FIFOs o Rx and Tx DMA channels 16-bit PWM with seven output channels Multiple GPIO pins Processing ARM Cortex-M3 processor, operating from an internal 80 MHz system clock Two 128 kb Flash/EE memory, 32 kb SRAM In-circuit download and debug via serial wire On-chip MDIO download capability On-Chip Peripherals Three general-purpose timers Wake-up timer Watchdog timer 32-element programmable logic array (PLA) Packages and Temperature Range 6 mm 6 mm, 96-ball BGA package, 40 C to +85 C Tools Low cost development system Third-party compiler and emulator tool support Applications Optical networking 10 G, 40 G, and 100 G modules Industrial control and automation systems Smart sensors, precision instrumentation Base station systems MEMORY ORGANIZATION The ADuCM320 memory organization is described in this section. Features Cortex-M3 memory system features o Predefined memory map. o Support for bit-band operation for atomic operations. o Unaligned data access. ADuCM320 on-chip peripherals are accessed via memory mapped registers, situated in the bit-band region. User memory sizes options: o 32 kb SRAM o Two 128 kb Flash/EE memory On-chip kernel for manufacturer data and in-circuit download Rev. C Page 8 of 196 UG-498 VENDOR SPECIFIC PRIVATE PERIPHERAL BUS EXTERNAL PRIVATE PERIPHERAL BUS INTERNAL 0xFFFF FFFF 0xE xE00F FFFF 0xE xE003 FFFF 0xE xDFFF FFFF ADuCM320 MMRs 0xE000 EF00 0xE000 E000 EXTERNAL DEVICE 1GB (NOT AVAILABLE IN ADuCM320) 0xA x9FFF FFFF EXTERNAL RAM 1GB (NOT AVAILABLE IN ADuCM320) 0x x5FFF FFFF PERIPHERAL 0.5GB 0x400A FFFF ADuCM320 MMRs 0x x x3FFF FFFF SRAM 0.5GB 0x2000 7FFF ADuCM320 32kB SRAM 0x x x1FFF FFFF CODE 0.5GB 0x0004 0FFF ADuCM320 KERNEL SPACE 0x x Figure 2. Cortex-M3 Memory Map Diagram ADuCM kB FLASH/EE MEMORY 0x0003 FFFF 0x Rev. C Page 9 of 196 UG-498 CLOCKING ARCHITECTURE CLOCKING ARCHITECTURE FEATURES The ADuCM320 integrates two on-chip oscillators and circuitry for an external crystal and external clock source: LFOSC is a 32 khz low power internal oscillator that is used in low power modes. HFOSC is a 16 MHz internal oscillator that is used in active mode. This is the default input to the PLL. HFXTAL is a 16 MHz external crystal oscillator. External clock input (ECLKIN) via GPIO pin. Rev. C Page 10 of 196 UG-498 CLOCKING ARCHITECTURE BLOCK DIAGRAM ACLK (TO LV DIE, ADC) HFXTAL 16MHz OSC 0 80MHZ SPLL 1 CLKCON0[11] CLKCON5[3] I2C0 CDPCLK (CLKCON1[10:8]) PCLK CLKCON5[4] I2C1 01 CLKCON5[5] UART HFOSC 16MHz OSC 00 UCLK CDD2DCLK (CLKCON1[11]) CLKCON5[6] PCLK D2D ECLKIN P CLKCON5[0] SPI0 CLKCON5[1] CLKCON0[1:0] CDHCLK (CLKCON1[2:0]) HCLK SPI1 CORE LFOSC (INTERNAL) WATCHDOG TIMER PWM FLASH PCLK WAKE-UP TIMER T4CON[9:10] PCLK HCLK PCLK HCLK TIMER0CLK T0CON[5:6] TIMER1CLK T1CON[5:6] PCLK HCLK TIMER2CLK T2CON[5:6] Figure 3. Clocking Architecture Block Diagram Rev. C Page 11 of 196 UG-498 CLOCKING ARCHITECTURE OVERVIEW The system clock, UCLK, can be selected from a 16 MHz oscillator or from an 80 MHz PLL output (default). An external clock on P1.0 can also be used for test purposes. Internally, the system clock is divided into separate clocks: UCLK system clock HCLK for the flash, SRAM, and DMA PCLK for most peripherals ACLK for the analog section of the chip; this is based on PCLK output and goes to the low voltage analog die All ADC performanc
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