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Pareto-Optimal Design and Performance Mapping of Telecom Rectifier Concepts J. Biela and J.W. Kolar ETH Zurich, Power Electronic Systems aboratory Abstract
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Pareto-Optimal Design and Performance Mapping of Telecom Rectifier Concepts J. Biela and J.W. Kolar ETH Zurich, Power Electronic Systems aboratory Abstract In the course of the design of single-phase PFC rectifiers, the demand for a high efficiency η and a high power density ρ must be met at the same time. Depending on the weight on these two design criteria different topologies could be advantageous. However, a comprehensive comparison of the topologies is difficult, since a large number of parameters must be determined and constraints in different physical domains, as e.g. magnetic or thermal properties, and EMI issues must be considered. Therefore, in this paper an approach based on relatively simple analytical equations is presented for calculating the limiting curves of conventional, bridgeless and TCM resonant-transition single-phase PFC rectifiers in the ρ-η-plane. These Pareto-imits represent the Topology Performance Map of the considered topologies and allow a direct comparison of the achievable performance and the limitations with respect to power density and/or efficiency. I. INTRODUCTION Over the last decades, the development of power electronics systems was mainly targeting higher power densities ρ and a reduction of the realisation costs [] [4]. A power loss reduction and/or increase of the conversion efficiency η was only indirectly required, as the surface area available for power loss dissipation decreases with decreasing converter volume. However, due to environmental concerns, high efficiency is more and more important, so that today at least two design requirements, i.e. high power density and high efficiency, have to be met. This results in a multi-objective design optimisation, where a best possible compromise must be found between the two conflicting criteria, since a higher efficiency usually leads to a higher system volume, i.e. a lower power density. In the design process, a large number of parameters must be determined and constraints in different physical domains, as e.g. magnetic or thermal properties, and EMI issues must be considered. This is complicated by the fact that many of the design parameters take influence not only on a single design aspect but on different con- 00% η M Max. Efficiency 0% η Feasible Performance Space Pareto-Front Efficiency kw [ dm] 3 Max. Power ρ ρ a) Density M b) η A Power Density Topologies Fig. : a) Power density efficiency plane (ρ-η-plane), where the maximal efficiency η M and the maximal power density ρ M as well as the ρ-η-pareto-front are shown. The Pareto-Front defines the maximal achievable performance for a compromise between power density and efficiency. b) System Performance Map, which shows the ρ-η-pareto- Fronts of different converter topologies. B C ρ verter properties as given e.g. the switching frequency, which influences the losses in the semiconductors, the cooling system, the design of the magnetics, etc. Accordingly, the set of parameter values which results in an optimal design is difficult to identify. Based on multi-domain converter models [3], [5] [7], an optimal mapping of the design parameters into the system Performance Space could be performed as described in [8]. There, different design criteria or quality indices could be considered and/or the best compromise of the required system level performances could be determined. Such an optimisation has been performed for telecom power supplies in [3], [4] or for single-phase bridgeless PFC rectifiers in [8], [9]. There, however only a single design criteria (either power density or efficiency) has been maximised, i.e. a - dimensional (D) optimisation has been performed. With an D optimisation, the maximal achievable efficiency and the maximal achievable power density can be identified for a given set of technologies, i.e. for unipolar/bipolar semiconductor switches, core materials, foil/electrolytic capacitors, etc. By simultaneously optimising the efficiency and the power density with different weights a performance limit and/or Pareto-Front could be determined in the ρ-η-plane (cf. Fig. a) [8]. The Pareto-Front directly indicates e.g. the maximal achievable efficiency for a required power density or shows how much the efficiency would be sacrificed in case the power density would have to be increased. In case the Pareto-imits of e.g. single-phase rectifier topologies would be known the performance of different concepts could be directly compared. This would allow to immediately identify the concept best suited for satisfying a given power density and efficiency requirement (cf. Fig. b). In alternative to optimising the systems with different weights, the Pareto-Front also could be approximated directly by relatively simple analytical models as will be shown in this paper for single-phase PFC rectifiers in the 2 power range of a few kilowatts. There, the standard PFC boost rectifier, a bridgeless converter and a resonanttransition (i.e. zero voltage switching), triangular current mode (TCM) PFC rectifier are considered and a Topology Performance Map is derived. First, the considered topologies are shortly discussed with respect to efficiency and power density in section II. Thereafter, the equations for calculating approximations of the Pareto-imit are presented in section III. The Pareto-imits of the different rectifier concepts are calculated in section IV. There, also experimental systems for validating the calculations and measurement results are presented. u N u N D D 2 D 3 D 4 CM DM D 5 UO + S C O U O D D 2 + C O R a) R II. SINGE-PHASE PFC RECTIFIER TOPOOGIES With the specifications of a converter system given, one of the first steps in the design process is the selection of the converter topology. For single-phase PFC rectifiers numerous topologies are described in literature. The most common concepts are shown in Fig. 2, where the simplest topology is the conventional PFC boost rectifier. However, this converter requires the largest silicon area for achieving a high efficiency as shown in Fig. 3. There, the required chip area for the MOSFET and the number of diodes is shown for the case that all converters have the same conduction losses. All diodes, which are only commutated with mains frequency (D -D 4 in Fig. 2a and D 2 &D 4 in Fig. 2c), are replaced by MOSFETs used as synchronous rectifiers in order to reduce the conduction losses. With the bridgeless PFC rectifier the smallest amount of silicon area, which is proportional to costs, is required for achieving a high efficiency. Consequently, this topology has been used in [9] to optimise a single-phase PFC rectifier for maximal efficiency. There, an efficiency of 99.3% has been achieved at a relatively low switching frequency of 8kHz, which is necessary to limit the switching losses. Due to the low switching frequency, the volume of the boost inductor is large resulting in a relatively low power density of.35kw/dm 2. The hard switching operation of the bridgeless PFC rectifier as well as of the conventional concept and the AC-switch PFC rectifier is a fundamental limitation, since the parasitic capacitances of the MOSFETs and the boost diode are causing losses at the MOSFET turn on. Besides the higher switching losses, this also prevents replacing the fast commutated freewheeling diodes with synchronous rectifiers, since the MOSFETs employed instead of the diodes exhibit a relatively large nonlinear capacitance, which would cause large turn-on current peaks resulting in even higher switching and total losses. Consequently, it is not possible to achieve a high power density and a high efficiency at the same time as will be demonstrated later with the help of Pareto Fronts, which clearly show the limits of the hard switching concepts in the ρ-η-plane. In order to avoid the capacitive losses occurring for hard switching, a Triangular Current Mode (TCM) u N u N C CM, C CM,2 S 2 S S S 2 S 4 S3 S S 2 D D 2 D 3 D 4 Fig. 2: Schematics of the conventional (a), the bridgeless with integrated CM-filter [8] (b), the AC-switch (c) and the triangular current mode (TCM) resonant-transition PFC rectifier with synchronous rectification [0] (d) are shown. The bridgeless PFC rectifier also could be realised with clamping diodes instead of capacitors C CM and C CM2 [] Conventional Bridgeless PFC Clamping Diodes Bridgeless PFC Integr. CM Fitler Bridgeless PFC AC-Switch MOSFET Area TCM Resonant- Transition PFC Conventional S 6 S 5 Bridgeless PFC Clamping Diodes + + Bridgeless PFC Integr. CM Fitler C O C O No. of Diodes U O U O Bridgeless PFC AC-Switch TCM Resonant- Transition PFC Fig. 3: Total MOSFET chip area for equal conduction losses of the topologies given in Fig. 2. Additionally, the quantity of required fast recovery diodes (SiC) is shown. There, D -D 4 in Fig. 2a) and D 2 & D 4 in Fig. 2c) are replaced by MOSFETs (synchronous rectifiers). resonant-transition single-phase PFC rectifier with a switching scheme according to Fig. 4 has been proposed [0], [2] [4]. At the top of this figure an equivalent circuit of the converter given in Fig. 2d) with only a single b) R c) R d) 3 i I S I AVG,t b) I R U O u S 2 S 2 3 T On T RT S 2 + U O u N S u C a) c) i i i T Off T P Zoomed View C P2 C P Connection due to S 5 turned on uc T R T T Rv RT2 i C O I AVG,t,N I AVG Fig. 4: a) One leg of the TCM resonant-transition PFC rectifier with nonlinear parasitic capacitors C P ν and b) waveforms of the inductor current i n and of the voltage u C across the lower MOSFET. half bridge leg (e.g. MOSFETs S and S 2 in Fig. 2d) for shaping the input current is shown. This equivalent circuit is valid for the positive mains cycle, where switch S 5 is constantly turned on and not shown in Fig. 4. In Fig. 4b) the control signals, the voltage across MOSFET S, and the inductor current i are shown for one switching period T P. The turn-off current I S of switch S is always chosen such, that the energy stored in inductor is large enough to increase voltage u C up to U O in order to enable ZVS turn on of switch S 2 after the resonant transition time T RT. With S 2 turned on, the energy stored in is transferred to the output capacitor t 0ms t t t t and S 2 acts as synchronous rectifier. Due to capacitors C P and especially C P 2, which shows a large capacitance for u C U O, current i in reverses after the time interval T off, so that again energy is stored in for a resonant-transition of u C down to zero. Assuming, that the mains voltage u N is smaller than U O /2 and neglecting losses, switch S 2 can be turned off at the zero crossing of i (i.e. at T R =0 in Fig. 4b) and due to the resonance of and C P C P 2 voltage u C reaches zero. Shortly thereafter switch S is turned on at zero voltage and the new cycle starts. In case u N U O /2, the resonance of and C P C P 2 is not enough to bring u C down to zero. Therefore, switch S 2 is kept turned on for time T R after T off and i reverses, so that finally the negative amplitude of i is increased as shown in Fig. 4. Time T R is chosen such, that enough energy is stored in for decreasing u C down to zero. As soon as i is equal to I R or after time T R, switch S 2 is turned off and u C resonates down to zero and S is turn on at ZVS condition. With this control scheme, the boost diodes can be replaced with synchronous rectifier MOSFETs without causing additional capacitive switching losses. This allows a significant reduction of the conduction losses in the semiconductors. However, the RMS currents in the boost inductor and in switches S /S 2 are larger than for the conventional PFC rectifier, as for u N U O /2 an additional negative current I R for achieving ZVS must be generated. With an increased I R also I S must be increased in order not to change I AV G,t, which is the average current during a switching period. This I AV G,t should show a sinusoidal time behaviour equal to I AV G,t,N as shown in Fig. 4c) and/or its average over half a mains cycle should be equal to the average mains current I AV G required for the desired output power. The larger RMS current could be compensated concerning the losses by increasing the chip area of S /S 2 and/or by reducing the R DSon and consequently the conduction losses. However, for a larger chip area again the RMS current values must be increased as the parasitic capacitances C P and C P 2 have a larger value. Furthermore, the gate drive losses increase as the gate charge increases with the chip area. Thus, there is an optimal value for the chip area resulting in minimal overall losses as will be shown below. The MOSFETs S -S 4 connected to an inductor in Fig. 2d) are operating at a high switching frequency and due to the resonant-transition with ZVS conditions. With these MOSFETs the input current is shaped. The return path for the inductor currents is provided by MOSFETs S 5 and S 6, which change their switching state at each zero crossing of the mains voltage, i.e. at very low frequency. This common return path used for all fast switching legs simplifies the control and reduces the circuit complexity. Due the return path operating at low frequency, the output of the rectifier is always connected to the mains. Consequently, the potential of the output voltage with respect to ground varies only twice during one mains 4 cycle, so that the generated CM current is relatively small. By interleaving several stages also the DM input ripple could be decreased significantly, so that only a small EMI filter is necessary. Further details about the synchronisation of interleaved bridge legs can be found in [5]. Details about the EMI behaviour of the bridgeless PFC rectifier can be found in [8]. There, a setup with clamping diodes and one with integrated CM-filter has been investigated and measurement results for the bridgeless PFC rectifier are presented. The MOSFET area for the TCM resonant-transition PFC rectifier shown in Fig. 3 depends on the forward voltage drop of the boost diode, the input current (modulation index) and the specific on-resistance of the MOSFET. In order to obtain the same conduction losses for a 3kW PFC rectifier operating at 230V mains voltage and a specific on resistance of 25mΩcm 2, for the TCM rectifier in total.2 times the MOSFET chip area of the bridgeless PFC rectifier with integrated CM-filter would be required. In Fig. 3 for the TCM rectifier it is assumed that the MOSFETs have the same chip area as the bridgeless PFC rectifier with integrated CM-filter, i.e a factor of 2 between the areas is shown. This results in the same conduction losses at low line voltage, but higher efficiency of the TCM rectifier at u N =230V. III. CACUATION OF THE ρ-η-pareto-imits OF DIFFERENT PFC RECTIFIER CONCEPTS For determining the limiting curves in the ρ-η-plane and/or the Feasible Performance Space [8], [6], in the following mathematical expressions for the losses and the volumes of the components of the single-phase PFC rectifier topologies discussed in section 2 are derived. These expressions are relatively simple approximations but nevertheless allow an identification of the limits and also of the relative performance of the different topologies. In contrast to the equations presented in [8], where a direct relation between the power density and the efficiency for the bridgeless PFC rectifier has been derived, here the losses and the volumes are calculated in dependency on the switching frequency and then a parametric plot of the limiting curve is performed. This simplifies the calculation of the Pareto-Front significantly and allows to easily add additional volume and/or loss contributors. A. Power Semiconductors First, the losses in the power MOSFETs and the diodes are calculated in dependency of the operating frequency based on general equations for the conventional PFC rectifier. Based on this, the loss equations for the different topologies are derived. For the loss equations, the RMS and the average currents in the devices are required. These can be calculated with I RMS,N = P IN U N I RMS,S = I AV G,S = 2 π 2M ÎN I RMS,BD = I AV G,BD = 2M ÎN I AV G,RD = π ÎN 2 4 3πM ÎN 4 3πM ÎN I RMS,RD = 2 I RMS,N with the modulation index M = U O /ÛN. Currents I RMS,S /I AV G,S are the RMS and the average current in the switch, I RMS,BD /I AV G,BD the RMS and the average current in the boost diode and I RMS,RD /I AV G,RD are the characteristic current values of the rectifier diodes. These equations are all for the conventional boost PFC rectifier and used in the following to determine the losses for the different topologies. There, first the conventional PFC is considered and based on the results the losses for the other topologies are determined. The conduction losses in the boost diode are P V,BD = U F,BD I AV G,BD + R D,BD I 2 RMS,BD () with R D,BD /A Chip,BD. There, U FB D is the forward voltage drop and R D,BD the differential resistance of the diode. The differential resistance is linearly dependent on the chip area of the diode A Chip,BD, which also determines the value of the parasitic boost diode capacitance. This parasitic capacitance must be charged during turnon of the boost switch and generates switching losses in the boost switch. The larger the diode chip area is, the lower are R D,BD and the conduction losses, but the higher are the switching losses in the MOSFET. Consequently, there is an optimal value for A Chip,BD resulting in minimal losses. The calculation of the optimal area will be shown below. In order to achieve a high efficiency and a compact design, switching losses should be minimised, so that it is assumed here that SiC Schottky diodes are utilised as boost diode [7] [9]. The conduction losses of the rectifier diodes P V,RD can be calculated analogously and the switching losses are negligible. The conduction losses in the MOSFET can simply be calculated with the on-resistance R DSon and the RMS current. The switching losses are mainly determined by the output capacitance of the MOSFET and the capacitance of the boost diode, which are both discharged via the MOSFET during turn-on. The additional switching losses caused during the commutation of the inductive current are relatively small if a high efficiency is desired, since the time for the commutation decreases linearly with an increasing chip area of the MOSFET. As for a high efficiency a large chip area is required, the commutation losses become relatively small in comparison to the losses due to the output capacitance, which increase with 5 osses Boost U O P O P V,Topt Α Chip,M,opt R th2 f p3 R th f p f p2 Chip Area Fig. 5: Dependency of the sum of conduction and capacitive switching losses of a power MOSFET on the chip area A Chip,M. The capacitive switching losses are due to the output capacitance C oss. Parameter: Switching frequency f P and thermal resistance R th. A larger chip area reduces the conduction losses (R DSon /A Chip,M ) but results in increased capacitive losses (C P A Chip,M ). Accordingly, depending on f P minimum total losses are achieved for a chip area A Chip,M,opt. For higher thermal resistance R th2 R th and/or higher junction temperature and on-resistance, the loss minimum is shifted to higher chip areas but despite the larger chip area higher total losses do occur. (Similar relations can be shown for A Chip,BD.) the chip area. Moreover, by decreasing the gate drive resistor, the time for turning on decreases. Therefore, the MOSFET losses are approximately given by P V,T = R DSon I 2 RMS,S + f P (C eq,m + C eq,bd ) U 2 O 2 with R DSon A Chip,M and C eq,ν A Chip,ν. There C eq,m is a constant equivalent capacitance, which results in the same switching losses as the voltage dependent output capacitance C P of the switching MOSFETs. The voltage dependency of C P could be approximated by C P = C 0 UO /u DS with C 0 = C P at U O. This results in W CP = 2/3 C 0 UO 2 for the energy stored in the output capacitance at a blocking voltage U
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