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FUJITSU SEMICONDUCTOR DATA SHEET DS501-00015-4v0-E Memory FRAM 64 K (8 K × 8) Bit SPI MB85RS64V ■ DESCRIPTION MB85RS64V is a FRAM (Ferroelectric Random…
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FUJITSU SEMICONDUCTOR DATA SHEET DS501-00015-4v0-E Memory FRAM 64 K (8 K × 8) Bit SPI MB85RS64V ■ DESCRIPTION MB85RS64V is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 8,192 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS64V adopts the Serial Peripheral Interface (SPI). The MB85RS64V is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85RS64V can be used for 1012 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. MB85RS64V does not take long time to write data like Flash memories or E2PROM, and MB85RS64V takes no wait time. ■ FEATURES ã Bit configuration : 8,192 words × 8 bits ã Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) ã Operating frequency : 20 MHz (Max) ã High endurance : 1012 times / byte ã Data retention : 10 years ( + 85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C) ã Operating power supply voltage : 3.0 V to 5.5 V ã Low power consumption : Operating power supply current 1.5 mA (Typ@20 MHz) Standby current 10 μA (Typ) ã Operation ambient temperature range : − 40 °C to + 85 °C ã Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.9 MB85RS64V ■ PIN ASSIGNMENT (TOP VIEW) CS 1 8 VDD SO 2 7 HOLD WP 3 6 SCK GND 4 5 SI (FPT-8P-M02) ■ PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name Functional description Chip Select pin This is an input pin to make chip select. When CS is the “H” level, device is in deselect 1 CS (standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time. When CS is the “L” level, device is in select (active) status. CS has to be the “L” level before inputting op-code. The Chip Select pin is pulled up internally to the VDD pin. Write Protect pin This is a pin to control writing to a status register. The writing of status register (see “■ 3 WP STATUS REGISTER”) is protected in related with WP and WPEN. See “■WRITING PROTECT” for detail. Hold pin This pin is used to interrupt serial input/output without making chip deselect. When 7 HOLD HOLD is the “L” level, hold operation is activated, SO becomes High-Z, and SCK and SI become don’t care. While the hold operation, CS shall be retained the “L” level. Serial Clock pin 6 SCK This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. Serial Data Input pin 5 SI This is an input pin of serial data. This inputs op-code, address, and writing data. Serial Data Output pin 2 SO This is an output pin of serial data. Reading data of FRAM memory cell array and status register are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 GND Ground pin 2 DS501-00015-4v0-E MB85RS64V ■ BLOCK DIAGRAM SI Serial-Parallel Converter Row Decoder FRAM Cell Array 8,192 ✕ 8 Address Counter CS FRAM Control Circuit SCK Status Register HOLD Column Decoder/Sense Amp/ Write Amp WP Data Register SO Parallel-Serial Converter DS501-00015-4v0-E 3 MB85RS64V ■ SPI MODE MB85RS64V corresponds to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) . CS SCK SI 7 6 5 4 3 2 1 0 MSB LSB SPI Mode 0 CS SCK SI 7 6 5 4 3 2 1 0 MSB LSB SPI Mode 3 4 DS501-00015-4v0-E MB85RS64V ■ SERIAL PERIPHERAL INTERFACE (SPI) MB85RS64V works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use. SCK MOSI MISO SO SI SCK SO SI SCK SPI MB85RS64V MB85RS64V Microcontroller CS HOLD CS HOLD SS1 SS2 HOLD1 HOLD2 MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select System Configuration with SPI Port SO SI SCK Microcontroller MB85RS64V CS HOLD System Configuration without SPI Port DS501-00015-4v0-E 5 MB85RS64V ■ STATUS REGISTER Bit No. Bit Name Function Status Register Write Protect This is a bit composed of nonvolatile memories (FRAM). WPEN protects 7 WPEN writing to a status register (see “■ WRITING PROTECT”) relating with WP input. Writing with the WRSR command and reading with the RDSR com- mand are possible. Not Used Bits These are bits composed of nonvolatile memories, writing with the WRSR 6 to 4 ⎯ command is possible. These bits are not used but they are read with the RDSR command. Block Protect 3 BP1 This is a bit composed of nonvolatile memory. This defines size of write protect block for the WRITE command (see “■ BLOCK PROTECT”). Writ- 2 BP0 ing with the WRSR command and reading with the RDSR command are possible. Write Enable Latch This indicates FRAM Array and status register are writable. The WREN command is for setting, and the WRDI command is for resetting. With the RDSR command, reading is possible but writing is not possible with the 1 WEL WRSR command. WEL is reset after the following operations. After power ON. After WRDI command recognition. At the rising edge of CS after WRSR command recognition. At the rising edge of CS after WRITE command recognition. 0 0 This is a bit fixed to “0”. ■ OP-CODE MB85RS64V accepts 7 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command are not performed. Name Description Op-code WREN Set Write Enable Latch 0000 0110B WRDI Reset Write Enable Latch 0000 0100B RDSR Read Status Register 0000 0101B WRSR Write Status Register 0000 0001B READ Read Memory Code 0000 0011B WRITE Write Memory Code 0000 0010B RDID Read Device ID 1001 1111B 6 DS501-00015-4v0-E MB85RS64V ■ COMMAND ã WREN The WREN command sets WEL (Write Enable Latch) . WEL shall be set with the WREN command before writing operation (WRSR command and WRITE command) . CS 0 1 2 3 4 5 6 7 SCK SI Invalid 0 0 0 0 0 1 1 0 Invalid High-Z SO ã WRDI The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRITE command and WRSR command) are not performed when WEL is reset. CS 0 1 2 3 4 5 6 7 SCK SI Invalid 0 0 0 0 0 1 0 0 Invalid High-Z SO DS501-00015-4v0-E 7 MB85RS64V ã RDSR The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid during this time. SO is output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising of CS. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 1 Invalid Data Out High-Z SO Invalid MSB LSB ã WRSR The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0 is ignored. The WP signal level shall be fixed before performing the WRSR command, and do not change the WP signal level until the end of command sequence. CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Instruction Data In SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 MSB LSB High-Z SO 8 DS501-00015-4v0-E MB85RS64V ã READ The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ are input to SI. The 3-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by con- tinuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK 16-bit Address OP-CODE SI 0 0 0 0 0 0 1 1 X X X 12 11 10 5 4 3 2 1 0 Invalid MSB LSB MSB Data Out LSB High-Z SO 7 6 5 4 3 2 1 0 Invalid ã WRITE The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address and 8 bits of writing data are input to SI. The 3-bit upper address bit is invalid. When 8 bits of writing data is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command. However, if you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over to the starting address, and writing cycle keeps on infinitely. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK 16-bit Address Data In OP-CODE SI 0 0 0 0 0 0 1 0 X X X 12 11 10 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB LSB MSB LSB High-Z SO DS501-00015-4v0-E 9 MB85RS64V ã RDID The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to SCK. The SI value is invalid during this time. SO is output synchronously to a falling edge of SCK. The output is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/ Product ID (2nd Byte). In the RDID command, SO holds the output state of the last bit in 32-bit Device ID until CS is risen. CS 0 1 2 3 4 5 6 7 8 9 10 11 31 32 33 34 35 36 37 38 39 SCK SI 1 0 0 1 1 1 1 1 Invalid Data Out Data Out High-Z SO 31 30 29 28 8 7 6 5 4 3 2 1 0 MSB LSB bit 7 6 5 4 3 2 1 0 Hex Manufacturer ID 0 0 0 0 0 1 0 0 04H Fujitsu Continuation code 0 1 1 1 1 1 1 1 7FH Proprietary use Density Hex Product ID (1st Byte) 0 0 0 0 0 0 1 1 03H Density: 00011B = 64kbit Proprietary use Hex Product ID (2nd Byte) 0 0 0 0 0 0 1 0 02H 10 DS501-00015-4v0-E MB85RS64V ■ BLOCK PROTECT Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register. BP1 BP0 Protected Block 0 0 None 0 1 1800H to 1FFFH (upper 1/4) 1 0 1000H to 1FFFH (upper 1/2) 1 1 0000H to 1FFFH (all) ■ WRITING PROTECT Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN, WP as shown in the table. WEL WPEN WP Protected Blocks Unprotected Blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected ■ HOLD OPERATION Hold status is retained without aborting a command if HOLD is the “L” level while CS is the “L” level. The timing for starting and ending hold status depends on the SCK to be the “H” level or the “L” level when a HOLD pin input is transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H” level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become don’t care. And, SO becomes High-Z while reading command (RDSR, READ). If CS is rising during hold status, a command is aborted. In case the command is aborted before its recognition, WEL holds the value before transition to HOLD status. CS SCK HOLD Hold Condition Hold Condition DS501-00015-4v0-E 11 MB85RS64V ■ ABSOLUTE MAXIMUM RATINGS Rating Parameter Symbol Unit Min Max Power supply voltage* VDD − 0.5 + 6.0 V Input voltage* VIN − 0.5 VDD + 0.5 ( ≤ 6.0) V Output voltage* VOUT − 0.5 VDD + 0.5 ( ≤ 6.0) V Operation ambient temperature TA − 40 + 85 °C Storage temperature Tstg − 55 + 125 °C *:These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Value Parameter Symbol Unit Min Typ Max Power supply voltage* VDD 3.0 ⎯ 5.5 V Input high voltage* VIH VDD × 0.8 ⎯ VDD + 0.3 V Input low voltage* VIL − 0.3 ⎯ VDD × 0.2 V Operation ambient temperature TA − 40 ⎯ + 85 °C *:These parameters are based on the condition that VSS is 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. 12 DS501-00015-4v0-E MB85RS64V ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) Value Parameter Symbol Condition Unit Min Typ Max 0 ≤ CS VDD ⎯ ⎯ 200 CS = VDD ⎯ ⎯ 10 Input leakage current |ILI| μA WP, HOLD, SCK, ⎯ ⎯ 10 SI = 0 V to VDD Output leakage current |ILO| SO = 0 V to VDD ⎯ ⎯ 10 μA Operating power supply current IDD SCK = 20 MHz ⎯ 1.5 2.5 mA Standby current ISB SCK = SI = CS = VDD ⎯ 10 20 μA Output high voltage VOH IOH = −2 mA VDD − 0.5 ⎯ VDD V Output low voltage VOL IOL = 2 mA VSS ⎯ 0.4 V Pull up resistance for CS RP ⎯ 28 50 180 kΩ DS501-00015-4v0-E 13 MB85RS64V 2. AC Characteristics Value Parameter Symbol Unit Min Max SCK clock frequency fCK 0 20 MHz Clock high time tCH 25 ⎯ ns Clock low time tCL 25 ⎯ ns Chip select set up time tCSU 10 ⎯ ns Chip select hold time tCSH 10 ⎯ ns Output disable time tOD ⎯ 20 ns Output data valid time tODV ⎯ 20 ns Output hold time tOH 0 ⎯ ns Deselect time tD 60 ⎯ ns Data rising time tR ⎯ 50 ns Data falling time tF ⎯ 50 ns Data set up time tSU 5 ⎯ ns Data hold time tH 5 ⎯ ns HOLD set up time tHS 10 ⎯ ns HOLD hold time tHH 10 ⎯ ns HOLD output floating time tHZ ⎯ 20 ns HOLD output active time tLZ ⎯ 20 ns AC Test Condition Power supply voltage : 3.0 V to 5.5 V Operation ambient temperature : − 40 °C to + 85 °C Input voltage magnitude : VDD × 0.1 to VDD × 0.9 Input rising time : 5 ns Input falling time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 14 DS501-00015-4v0-E MB85RS64V AC Load Equivalent Circuit 5.5 V Output 30 pF 3. Pin Capacitance Value Parameter Symbol Conditions Unit Min Max Output capacitance CO VDD = VIN = VOUT = 0 V ⎯ 10 pF Input capacitance CI f = 1 MHz, TA = + 25 °C ⎯ 10 pF DS501-00015-4v0-E 15 MB85RS64V ■ TIMING DIAGRAM ã Serial Data Timing tD CS tCSH tCSU tCH tCL tCH SCK tSU tH SI Valid in tODV tOH tOD High-Z High-Z SO : H or L ã Hold Timing CS SCK tHS tHS tHS tHS tHH tHH tHH tHH HOLD High-Z High-Z SO tHZ tLZ tHZ tLZ 16 DS501-00015-4v0-E MB85RS64V ■ POWER ON/OFF SEQUENCE tpd tf tr tpu VDD VDD 3.0 V 3.0 V VIH (Min) VIH (Min) 1.2 V 1.2 V VIL (Max) VIL (Max) GND GND CS CS VDD × 0.8 * CS : don't care CS VDD × 0.8 * CS * : CS (Max) VDD + 0.3 V Value Parameter Symbol Unit Condition Min Max CS level hold time at power OFF tpd 400 ⎯ ns ⎯ 0.1 ⎯ VDD = 5.0V ± 0.5V Operation CS level hold time at power ON tpu ms 0.6 ⎯ VDD = 3.3V ± 0.3V Operation Power supply falling time tf 200 ⎯ μs/V ⎯ 100 ⎯ VDD = 5.0V ± 0.5V Operation Power supply rising time tr μs/V 1 ⎯ VDD = 3.3V ± 0.3V Operation If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed. ■ FRAM CHARACTERISTICS Item Min Max Unit Parameter Read/Write Endurance* 1 10 12 ⎯ Times/byte Operation Ambient Temperature TA = + 85 °C 10 ⎯ Operation Ambient Temperature TA = + 85 °C Data Retention* 2 95 ⎯ Years Operation Ambient Temperature TA = + 55 °C ≥ 200 ⎯ Operation Ambient Temperature TA = + 35 °C *1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates with destructive readout mechanism. *2 : Minimun values define retention time of the first reading/writing data right after shipment, and these values are calculated by qualification results. DS501-00015-4v0-E 17 MB85RS64V ■ NOTE ON USE We recommend programming of the device after reflow. Data written before reflow cannot be guaranteed. ■ ESD AND LATCH-UP Test DUT Value ESD HBM (Human Body Model) ≥ |2000 V| JESD22-A114 compliant ESD MM (Machine Model) ≥ |200 V| JESD22-A115 compliant ESD CDM (Charged Device Model) ≥ |1000 V| JESD22-C101 compliant Latch-Up (I-test) MB85RS64VPNF-G-JNE1 ⎯ JESD78 compliant Latch-Up (Vsupply overvoltage test) ⎯ JESD78 compliant Latch-Up (Current Method) ⎯ Proprietary method Latch-Up (C-V Method) ≥ |200 V| Proprietary method ã Current method of Latch-Up Resistance Test Protection Resistor A IIN Test terminal VDD VDD (Max.Rating) + DUT VIN V - VSS Reference terminal Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm the latch up does not occur under IIN = ± 300 mA. In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be increased to the level that meets the specific requirement. 18 DS501-00015-4v0-E MB85RS64V ã C-V method of Latch-Up Resistance Test Protection Resistor A Test 1 2 terminal VDD SW VDD DUT + (Max.Rating) VIN V C - 200pF VSS Reference terminal Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is considered as one cycle. Repeat this process 5 times. However, if the latch-up condition occurs before completing 5 times, this test must be stopped immediately. ■ REFLOW CONDITIONS AND FLOOR LIFE [ JEDEC MSL ] : Moisture Sensitivity Level 3 (ISP/JEDEC J-STD-020D) ■ CURRENT STATUS ON CONTAINED RESTRICTED SUBSTANCES This product complies with the regulations of REACH Regulations, EU RoHS Directive and China RoHS. Please refer to the following web site for more details of current status on contained restricted substances in our products. http://www.fujitsu.com/global/services/microelectronics/environment/products/ DS501-00015-4v0-E 19 MB85RS64V ■ ORDERING INFORMATION Minimum shipping Part number Package Shipping form quantity 8-pin plastic SOP MB85RS64VPNF-G-JNE1 Tube ⎯* (FPT-8P-M02) 8-pin plastic SOP MB85RS64VPNF-G-JNERE1 Embossed Carrier tape 1500 (FPT-8P-M02) *: Please contact our sales office about minimum shipping quantity. 20 DS501-00015-4v0-E MB85RS64V ■ PACKAGE DIMENSION 8-pin plastic SOP Lead pitch 1.27 mm Package width × 3.9 mm × 5.05 mm package length Lead shape Gullwing Sealing method Plastic mold Mounting height 1.75 mm MAX Weight 0.06 g (FPT-8P-M02) 8-pin plastic SOP Note 1) *1 : These dimensions include resin protrusion. (FPT-8P-M02) Note 2) *2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. +0.25 +.010 +0.03 *1 5.05 –0.20 .199 –.008 0.22 –0.07 +.001 .009 –.003 8 5 *2 3.90±0.30 6.00±0.20 (.154±.012) (.236±.008) Details of A part 45° 1.55±0.20 (Mounting height) (.061±.008) 0.25(.010) 0.40(.016) 1 4 A 0~8° 1.27(.050) 0.44±0.08 0.13(.005) M (.017±.003) 0.50±0.20 0.15±0.10 (.020±.008) (.006±.004) 0.60±0.15 (Stand off) (.024±.006) 0.10(.004) Dimensions in mm (inches). C 2002-2012 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-5-10 Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ DS501-00015-4v0-E 21 MB85RS64V ■ MARKING [MB85RS64VPNF-G-JNE1] [MB85RS64VPNF-G-JNERE1] RS64V E11200 300 [FPT-8P-M02] 22 DS501-00015-4v0-E MB85RS64V ■ PACKING INFORMATION 1. Tube 1.1 Tube Dimensions ã Tube/stopper shape Tube Transparent polyet
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