Single Hot-Swap Power Controllers with Circuit Breaker and Power

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TPS2330 TPS2331 www.ti.com SLVS277G – MARCH 2000 – REVISED JULY 2013 SINGLE HOT-SWAP POWER CONTROLLERS WITH CIRCUIT BREAKER AND POWER-GOOD REPORTING Check…
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TPS2330 TPS2331 www.ti.com SLVS277G – MARCH 2000 – REVISED JULY 2013 SINGLE HOT-SWAP POWER CONTROLLERS WITH CIRCUIT BREAKER AND POWER-GOOD REPORTING Check for Samples: TPS2330, TPS2331 1FEATURES D OR PW PACKAGE ã Single-Channel High-Side MOSFET Driver (TOP VIEW) ã Input Voltage: 3 V to 13 V GATE 1 14 DISCH ã Output dV/dt Control Limits Inrush Current DGND 2 13 ENABLE TIMER 3 12 PWRGD ã Circuit-Breaker With Programmable 4 11 VREG FAULT Overcurrent Threshold and Transient Timer VSENSE 5 10 ISET ã Power-Good Reporting With Transient Filter AGND 6 9 AGND ISENSE 7 8 IN ã CMOS- and TTL-Compatible Enable Input NOTE: Terminal 13 is active-high on TPS2331. ã Low 5-μA Standby Supply Current (Max) ã Available in 14-Pin SOIC and TSSOP Package typical application ã –40°C to 85°C Ambient Temperature Range + VO VIN ã Electrostatic Discharge Protection 3 V–13 V IN ISET ISENSE GATE DISCH VREG VSENSE APPLICATIONS ã Hot-Swap/Plug/Dock Power Management AGND TPS2330 PWRGD ã Hot-Plug PCI, Device Bay DGND FAULT ã Electronic Circuit Breaker ENABLE TIMER DESCRIPTION The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush-current control, output-power status reporting, and the ability to discriminate between load transients and faults, are critical requirements for hot-swap applications. The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the device is off at start-up and confirm the status of the output voltage rails during operation. An internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pump controls both the rise times and fall times (dV/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period. Table 1. AVAILABLE OPTIONS PACKAGES (1) TA HOT-SWAP CONTROLLER DESCRIPTION PIN COUNT ENABLE ENABLE Dual-channel with independent OCP and adjustable PG 20 TPS2300IPW TPS2301IPW Dual-channel with interdependent OCP and adjustable PG 20 TPS2310IPW TPS2311IPW –40°C to 85°C TPS2320ID TPS2321ID Dual-channel with independent OCP 16 TPS2320IPW TPS2321IPW TPS2330ID TPS2331ID Single-channel with OCP and adjustable PG 14 TPS2330IPW TPS2331IPW (1) The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2331IPWR). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TPS2330 TPS2331 SLVS277G – MARCH 2000 – REVISED JULY 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM IN ISET ISENSE GATE DISCH VREG PREREG Clamp dv/dt Rate Protection Circuit Charge 50 µA Pump Breaker Pulldown FET UVLO and Circuit Breaker AGND Power Up VSENSE 75 µA PWRGD DGND Deglitcher FAULT Logic ENABLE Deglitcher TIMER Table 2. Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. AGND 6, 9 I Analog ground, connects to DGND as close as possible DGND 2 I Digital ground DISCH 14 O Discharge transistor ENABLE/ENABLE 13 I Active-low (TPS2330) or active-high enable (TPS2331) FAULT 11 O Overcurrent fault, open-drain output GATE 1 O Connects to gate of high-side MOSFET IN 8 I Input voltage ISENSE 7 I Current-sense input ISET 10 I Adjusts circuit-breaker threshold with resistor connected to IN PWRGD 12 O Open-drain output, asserted low when VSENSE voltage is less than reference. TIMER 3 O Adjusts circuit-breaker deglitch time VREG 4 O Connects to bypass capacitor, for stable operation VSENSE 5 I Power-good sense input 2 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: TPS2330 TPS2331 TPS2330 TPS2331 www.ti.com SLVS277G – MARCH 2000 – REVISED JULY 2013 DETAILED DESCRIPTION DISCH – DISCH should be connected to the source of the external N-channel MOSFET transistor connected to GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as reference- voltage connection for internal gate-voltage-clamp circuitry. ENABLE or ENABLE – ENABLE for TPS2330 is active-low. ENABLE for TPS2331 is active-high. When the controller is enabled, GATE voltage powers up to turn on the external MOSFETs. When the ENABLE pin is pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 μs, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than 5 μA. FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low. In order to turn the device back on, either the enable pin must be toggled or the input power must be cycled. GATE – GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled, internal charge-pump circuitry pulls this pin up by sourcing approximately 15 μA. The turnon slew rates depend on the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced by connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during power up. The charge-pump circuitry generates gate-to-source voltages of 9 V–12 V across the external MOSFET transistor. IN – IN should be connected to the power source driving the external N-channel MOSFET transistor connected to GATE. The TPS2330/31 draws its operating current from IN, and remains disabled until the IN power supply has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation. ISENSE, ISET – ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the magnitude of the current that generates an overcurrent fault, through an external resistor connected to ISET. An internal current source draws 50 μA from ISET. With a sense resistor from IN to ISENSE, which is also connected to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE is pulled below ISET. To ensure proper circuit breaker operation, VI(ISENSE) and VI(ISET) should never exceed VI(IN). PWRGD – PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain output and is pulled low during an undervoltage condition. To minimize erroneous PWRGD responses from transients on the voltage rail, the voltage sense circuit incorporates a 20-μs deglitch filter. When VSENSE is lower than the reference voltage (about 1.23 V), PWRGD is active-low to indicate an undervoltage condition on the power-rail voltage. PWRGD may not correctly report power conditions when the device is disabled because there is no gate drive power for the PWRGD output transistor in the disable mode, or, in other words, PWRGD is floating. Therefore, PWRGD is pulled up to its pullup power supply rail in disable mode. TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering. VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-μF ceramic capacitor should be connected between VREG and ground to aid in noise rejection. In this configuration, on disabling the device, the internal low-dropout regulator also is disabled, which removes power from the internal circuitry and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than 5.5 V, VREG and IN1 may be connected together. However, under these conditions, disabling the device may not place the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being bypassed, thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-μF ceramic capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1 μF to 10 μF. VSENSE – VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses a voltage below approximately 1.23 V, PWRGD is pulled low. Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS2330 TPS2331 TPS2330 TPS2331 SLVS277G – MARCH 2000 – REVISED JULY 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VALUE UNIT VI(IN1), VI(ISENSE), VI(VSENSE), VI(ISET), VI(ENABLE) –0.3 to 15 V Input voltage range VI(VREG) –0.3 to 7 V VO(GATE) –0.3 to 30 V Output voltage range VO(DISCH), VO(PWRGD), VO( FAULT ), VO(TIMER) –0.3 to 15 V I(GATE), I(DISCH) 0 to 100 mA Sink current range I(PWRGD), I(TIMER), I( FAULT ) 0 to 10 mA Operating virtual junction temperature range, TJ –40 to 100 °C Storage temperature range, Tstg –55 to 150 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to DGND. DISSIPATION RATING TABLE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C PACKAGE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING PW-14 755 mW 10.07 mW/°C 302 mW 151 mW D-14 613 mW 8.18 mW/°C 245 mW 123 mW RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VI(IN), VI(ISENSE), VI(VSENSE), VI(ISET) 3 13 VI Input voltage VI(VREG) 3 5.5 V VI(ISENSE), VI(ISET), VI(VSENSE) VI(IN) TJ Operating virtual junction temperature –40 100 °C 4 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: TPS2330 TPS2331 TPS2330 TPS2331 www.ti.com SLVS277G – MARCH 2000 – REVISED JULY 2013 ELECTRICAL CHARACTERISTICS over recommended operating temperature range (–40°C TA 85°C), 3V ≤ VI(IN1) ≤13 V, 3 V ≤ VI(IN2) ≤ 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GENERAL VI(ENABLE) = 5 V (TPS2331), II(IN) Input current, IN 0.5 1 mA VI( ENABLE ) = 0 V (TPS2330) Standby current (sum of currents into VI(ENABLE) = 0 V (TPS2331), II(stby) 5 μA IN, ISENSE, and ISET) VI( ENABLE ) = 5 V (TPS2330) GATE VG(GATE_3V) VI(IN) = 3 V 9 11.5 VG(GATE_4.5V) Gate voltage II(GATE) = 500 nA, DISCH open VI(IN) = 4.5 V 10.5 14.5 V VG(GATE_10.8V) VI(IN) = 10.8 V 16.8 21 VC(GATE) Clamping voltage, GATE to DISCH 9 10 12 V 3 V ≤ VI(IN) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V, IS(GATE) Source current, GATE 10 14 20 μA VI(GATE) = VI(IN) + 6 V 3 V ≤ VI(IN) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V, Sink current, GATE 50 75 100 μA VI(GATE) = VI(IN) VI(IN) = 3 V 0.5 tr(GATE) Rise time, GATE Cg to GND = 1 nF (1) VI(IN) = 4.5 V 0.6 ms VI(IN) = 10.8 V 1 VI(IN) = 3 V 0.1 tf(GATE) Fall time, GATE Cg to GND = 1 nF (1) VI(IN) = 4.5 V 0.12 ms VI(IN) = 10.8 V 0.2 TIMER V(TO_TIMER) Threshold voltage, TIMER 0.4 0.5 0.6 V Charge current, TIMER VI(TIMER) = 0 V 35 50 65 μA Discharge current, TIMER VI(TIMER) = 1 V 1 2.5 mA CIRCUIT BREAKER RISET = 1 kΩ 40 50 60 RISET = 400 Ω, TA = 25°C 14 19 24 VIT(CB) Threshold voltage, circuit breaker mV RISET = 1 kΩ, TA = 25°C 44 50 53 RISET = 1.5 kΩ, TA = 25°C 68 73 78 I(IB_ISENSE) Input bias current, ISENSE 0.1 5 μA VO(GATE) = 4 V 400 800 Discharge current, GATE mA VO(GATE) = 1 V 25 150 Propagation (delay) time, comparator Cg = 50 pF, 10-mV overdrive, tpd(CB) 1.3 μs inputs to gate output (50% to 10%), CTIMER = 50 pF ENABLE, ACTIVE LOW (TPS2330) VIH( ENABLE ) High-level input voltage, ENABLE 2 V VIL( ENABLE ) Low-level input voltage, ENABLE 0.8 V (2) RI( ENABLE ) Input pullup resistance, ENABLE See 100 200 300 kΩ VI( ENABLE ) increasing above stop threshold; td(off_ ENABLE ) Turnoff delay time, ENABLE 60 μs 100 ns rise time, 20 mV overdrive (1) VI( ENABLE ) decreasing below start threshold; td(on_ ENABLE ) Turnon delay time, ENABLE 125 μs 100 ns fall time, 20 mV overdrive (1) (1) Specified, but not production tested. 1V (2) Test IO of ENABLE at VI( ENABLE ) = 1 V and 0 V, then RI( ENABLE ) = I O_ 0V * I O_ 1V Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPS2330 TPS2331 TPS2330 TPS2331 SLVS277G – MARCH 2000 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (Continued) over recommended operating temperature range (–40°C TA 85°C), 3 V ≤VI(IN1) ≤13 V, 3 V ≤ VI(IN2) ≤ 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENABLE, ACTIVE HIGH (TPS2331) VIH(ENABLE) High-level input voltage, ENABLE 2 V VIL(ENABLE) Low-level input voltage, ENABLE 0.7 V RI(ENABLE) Input pulldown resistance, ENABLE 100 150 300 kΩ VI(ENABLE) increasing above start threshold; td(on_ENABLE) Turnon delay time, ENABLE 85 μs 100-ns rise time, 20-mV overdrive (1) VI(ENABLE) decreasing below stop threshold; td(off_ENABLE) Turnoff delay time, ENABLE 100 μs 100-ns fall time, 20-mV overdrive (1) PREREG V(VREG) PREREG output voltage 4.5 ≤ VI(IN) ≤ 13 V 3.5 4.1 5.5 V V(drop_PREREG) PREREG dropout voltage VI(IN) = 3 V 0.1 V VREG UVLO V(TO_UVLOstart) Output threshold voltage, start 2.75 2.85 2.95 V V(TO_UVLOstop) Output threshold voltage, stop 2.65 2.78 V Vhys(UVLO) Hysteresis 50 75 mV UVLO sink current, GATE VI(GATE) = 2 V 10 mA PWRGD1 and PWRGD2 VI(VSENSE) decreasing 1.22 VIT(ISENSE) Trip threshold, VSENSE 1.2 1.25 V 5 Hysteresis voltage, power-good Vhys 20 30 40 mV comparator VO(sat_PWRGD) Output saturation voltage, PWRGD IO = 2 mA 0.2 0.4 V Minimum VO(VREG) for valid power- IO = 100 μA, VO(PWRGD) = 1 V VO(VREG_min) 1 V good Input bias current, power-good VI(VSENSE) = 5.5 V 1 μA comparator Ilkg(PWRGD) Leakage current, PWRGD VO(PWRGD) = 13 V 1 μA VI(VSENSE) increasing, overdrive = 20 mV, tdr Delay time, rising edge, PWRGD 25 μs tr = 100 ns (1) VI(VSENSEx) decreasing, overdrive = 20 mV, tdf Delay time, falling edge, PWRGDx 2 μs tr = 100 ns (1) FAULT OUTPUT VO(sat_ FAULT ) Output saturation voltage, FAULT IO = 2 mA 0.4 V Ilkg( FAULT ) Leakage current, FAULT VO( FAULT ) = 13 V 1 μA DISCH I(DISCH) Discharge current, DISCH VI(DISCH) = 1.5 V, VI(VIN) = 5 V 5 10 mA VIH(DISCH) Discharge on high-level input voltage 2 V VIL(DISCH) Discharge on low-level input voltage 1 V (1) Specified, but not production tested. 6 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: TPS2330 TPS2331 TPS2330 TPS2331 www.ti.com SLVS277G – MARCH 2000 – REVISED JULY 2013 PARAMETER MEASUREMENT INFORMATION Load 12 W Load 12 W VI(ENABLE) 5 V/div VI(ENABLE) 5 V/div VO(GATE) 10 V/div VO(DISCH) VO(GATE) 5 V/div 10 V/div VO(DISCH) 5 V/div t – Time – 10 ms/div t – Time – 10 ms/div Figure 1. Turnon Voltage Transition Figure 2. Turnoff Voltage Transition No Capacitor on Timer No Capacitor on Timer VI(ENABLE) VI(ENABLE) 5 V/div 5 V/div VO(GATE) 10 V/div VO(GATE) 10 V/div VO(FAULT) VO(FAULT) 10 V/div 10 V/div IO(OUT) IO(OUT) 2 A/div 2 A/div t – Time – 5 ms/div t – Time – 1 ms/div Figure 3. Overcurrent Response: Figure 4. Overcurrent Response: an Overcurrent Enabled Into Overcurrent Load Load Plugged Into the Enabled Board Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPS2330 TPS2331 TPS2330 TPS2331 SLVS277G – MARCH 2000 – REVISED JULY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) No Capacitor on Timer No Capacitor on Timer VI(ENABLE) 5 V/div VI(IN) 10 V/div VO(GATE) VO(GATE) 10 V/div 10 V/div VO(FAULT) 10 V/div VO(OUT) 10 V/div II(IN) IO(OUT) 2 A/div 1 A/div t – Time – 1 ms/div t – Time – 5 ms/div Figure 5. Enabled Into Short Circuit Figure 6. Hot Plug VI(IN) No Capacitor on Timer 10 V/div VO(GATE) 10 V/div VO(OUT) 10 V/div IO(OUT) 1 A/div t – Time – 1 ms/div Figure 7. Hot Removal 8 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: TPS2330 TPS2331 TPS2330 TPS2331 www.ti.com SLVS277G – MARCH 2000 – REVISED JULY 2013 TYPICAL CHARACTERISTICS INPUT CURRENT (ENABLED) INPUT CURRENT (DISABLED) vs vs INPUT VOLTAGE INPUT VOLTAGE 52 15 IN = 5 V to 13 V IN = 5 V to 13 V TA = 85°C 51 TA = 85°C 14 TA = 25°C 50 13 TA = 25°C TA = –40°C II – Input Current – mA II – Input Current – nA 49 12 48 TA = 0°C 11 47 TA = 0°C 10 46 TA = –40°C 9 45 44 8 43 7 4 5 6 7 8 9 10 11 12 13 14 4 5 6 7 8 9 10 11 12 13 14 VI – Input Voltage – V VI – Input Voltage – V Figure 8. Figure 9. GATE OUTPUT VOLTAGE GATE VOLTAGE RISE TIME vs vs INPUT VOLTAGE GATE LOAD CAPACITANCE 22 18 CL(GATE) = 1000 pF IN = 12 V TA = 85°C TA = 25°C 20 TA = 25°C 15 tr – GATE Voltage Rise Time – ms VO – GATE Output Voltage – V TA = 0°C 18 12 TA = –40°C 16 9 14 6 12 3 10 0 2 3 4 5 6 7 8 9 10 11 12 0 3 6 9 12 VI – Input Voltage – V CL(GATE) – GATE Load Capacitance – nF Figure 10. Figure 11. Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPS2330 TPS2331 TPS2330 TPS2331 SLVS277G – MARCH 2000 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) GATE VOLTAGE FALL TIME GATE OUTPUT CURRENT vs vs GATE LOAD CAPACITANCE GATE VOLTAGE 4 15 IN = 12 V TA = 25°C 14.5 t f – GATE Voltage Fall Time – ms IO – GATE Output Current – mA 3 14 TA = –40°C TA = 85°C 13.5 TA = 25°C 2 13 TA = 0°C 12.5 1 12 11.5 IN = 13 V 0 11 0 3 6 9 12 14 15 16 17 18 19 20 21 22 23 24 CL(GATE) – GATE Load Capacitance – nF V – GATE Voltage – V Figure 12. Figure 13. CIRCUIT-BREAKER RESPONSE TIME LOAD VOLTAGE DISCHARGE TIME vs vs TIMER CAPACITANCE LOAD CAPACITANCE 12 320 IN = 12 V IN = 12 V t(res) – Circuit-Breaker Response Time – ms TA = 25°C 280 IO = 0 A t – Load Voltage Discharge Time – ms TA = 25°C 9 240 200 6 160 120 3 80 40 0 0 0 0.2 0.4 0.6 0.8 1 0 100 200 300 400 500 CTIMER – TIMER Capacitance – nF CL – Load Capacitance – mF Figure 14. Figure 15. 10 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: TPS2330 TPS2331 TPS2330 TPS2331 www.ti.com SLVS277G – MARCH 2000 – REVISED JULY 2013 TYPICAL CHARACTERISTICS (continued) UVLO START AND STOP THRESHOLDS PWRGD INPUT THRESHOLD vs vs TEMPERATURE TEMPERATURE 2.9 1.27 Vref – UVLO Start and Stop Thresholds – V 2.88 1.26 Up VIT – PWRGD Input Threshold – V 2.86 Start 2.84 1.25 2.82 1.24 2.8 1.23 Down 2.78 Stop 2.76 1.22 2.74 1.21 2.72 2.7 1.20 –45–35 –25–15 –5 5 15 25 35 45 55 65
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