Part I Introduction. Part II Combinational logic CONTENTS. 1 The digital abstraction 3. 2 The practice of digital system design 22 - PDF

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CONTENTS Preface Acknowledgments page xv xx Part I Introduction 1 The digital abstraction Digital signals Digital signals tolerate noise Digital signals represent complex data
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CONTENTS Preface Acknowledgments page xv xx Part I Introduction 1 The digital abstraction Digital signals Digital signals tolerate noise Digital signals represent complex data Representing the day of the year Representing subtractive colors Digital logic functions VHDL description of digital circuits and systems Digital logic in systems 16 Summary 17 Bibliographic notes 18 Exercises 18 2 The practice of digital system design The design process Specification Concept development and feasibility Partitioning and detailed design Verification Digital systems are built from chips and boards Computer-aided design tools Moore s law and digital system evolution 34 Summary 36 Bibliographic notes 36 Exercises 37 Part II Combinational logic 3 Boolean algebra Axioms 43 vi 3.2 Properties Dual functions Normal form From equations to gates Boolean expressions in VHDL 51 Summary 54 Bibliographic notes 55 Exercises 55 4 CMOS logic circuits Switch logic Switch model of MOS transistors CMOS gate circuits Basic CMOS gate circuit Inverters, NANDs, and NORs Complex gates Tri-state circuits Circuits to avoid 76 Summary 77 Bibliographic notes 78 Exercises 78 5 Delay and power of CMOS circuits Delay of static CMOS gates Fan-out and driving large loads Fan-in and logical effort Delay calculation Optimizing delay Wire delay Power dissipation in CMOS circuits Dynamic power Static power Power scaling 100 Summary 101 Bibliographic notes 101 Exercises Combinational logic design Combinational logic Closure Truth tables, minterms, and normal form Implicants and cubes Karnaugh maps Covering a function 115 vii 6.7 From a cover to gates Incompletely specified functions Product-of-sums implementation Hazards 121 Summary 123 Bibliographic notes 124 Exercises VHDL descriptions of combinational logic The prime number circuit in VHDL A VHDL design entity The case statement The case? statement The if statement Concurrent signal assignment statements Selected signal assignment statements Conditional signal assignment statements Structural description The decimal prime number function A testbench for the prime number circuit Example: a seven-segment decoder 148 Summary 153 Bibliographic notes 154 Exercises Combinational building blocks Multi-bit notation Decoders Multiplexers Encoders Arbiters and priority encoders Comparators Shifters Read-only memories Read write memories Programmable logic arrays Data sheets Intellectual property 195 Summary 195 Bibliographic notes 196 Exercises Combinational examples Multiple-of-3 circuit 199 viii 9.2 Tomorrow circuit Priority arbiter Tic-tac-toe 207 Summary 214 Exercises 215 Part III Arithmetic circuits 10 Arithmetic circuits Binary numbers Binary addition Negative numbers and subtraction Multiplication Division 240 Summary 244 Exercises Fixed- and floating-point numbers Representation error: accuracy, precision, and resolution Fixed-point numbers Representation Operations Floating-point numbers Representation Denormalized numbers and gradual underflow Floating-point multiplication Floating-point addition/subtraction 260 Summary 265 Bibliographic note 265 Exercises Fast arithmetic circuits Carry look-ahead Booth recoding Wallace trees Synthesis notes 284 Summary 286 Bibliographic notes 287 Exercises Arithmetic examples Complex multiplication Converting between fixed- and floating-point formats 291 ix Floating-point format Fixed- to floating-point conversion Floating- to fixed-point conversion FIR filter 298 Summary 300 Bibliographic note 300 Exercises 300 Part IV Synchronous sequential logic 14 Sequential logic Sequential circuits Synchronous sequential circuits Traffic-light controller State assignment Implementation of finite-state machines VHDL implementation of finite-state machines 316 Summary 324 Bibliographic notes 324 Exercises Timing constraints Propagation and contamination delay The D flip-flop Setup- and hold-time constraints The effect of clock skew Timing examples Timing and logic synthesis 337 Summary 339 Bibliographic notes 340 Exercises Datapath sequential logic Counters A simpler counter Up/down/load counter A timer Shift registers A simple shift register Left/right/load (LRL) shift register Universal shifter/counter Control and data partitioning Example: vending machine FSM 357 x Example: combination lock 367 Summary 372 Exercises Factoring finite-state machines A light flasher Traffic-light controller 382 Summary 393 Exercises Microcode Simple microcoded FSM Instruction sequencing Multi-way branches Multiple instruction types Microcode subroutines Simple computer 420 Summary 427 Bibliographic notes 427 Exercises Sequential examples Divide-by-3 counter SOS detector Tic-tac-toe game Huffman encoder/decoder Huffman encoder Huffman decoder 442 Summary 448 Bibliographic note 448 Exercises 448 Part V Practical design 20 Verification and test Design verification Verification coverage Types of tests Static timing analysis Formal verification Bug tracking Test Fault models 456 xi Combinational testing Testing redundant logic Scan Built-in self-test (BIST) Characterization 460 Summary 461 Bibliographic notes 462 Exercises 462 Part VI System design 21 System-level design System design process Specification Pong DES cracker Music player Partitioning Pong DES cracker Music synthesizer 475 Summary 476 Bibliographic notes 477 Exercises Interface and system-level timing Interface timing Always valid timing Periodically valid signals Flow control Interface partitioning and selection Serial and packetized interfaces Isochronous timing Timing tables Event flow Pipelining and anticipatory timing Interface and timing examples Pong DES cracker Music player 493 Summary 493 Exercises 494 xii 23 Pipelines Basic pipelining Example pipelines Example: pipelining a ripple-carry adder Pipeline stalls Double buffering Load balance Variable loads Resource sharing 516 Summary 517 Bibliographic notes 518 Exercises Interconnect Abstract interconnect Buses Crossbar switches Interconnection networks 527 Summary 529 Bibliographic notes 529 Exercises Memory systems Memory primitives SRAM arrays DRAM chips Bit-slicing and banking memory Interleaved memory Caches 540 Summary 544 Bibliographic notes 545 Exercises 545 Part VII Asynchronous logic 26 Asynchronous sequential circuits Flow-table analysis Flow-table synthesis: the toggle circuit Races and state assignment 558 Summary 562 Bibliographic notes 563 Exercises 563 xiii 27 Flip-flops Inside a latch Inside a flip-flop CMOS latches and flip-flops Flow-table derivation of the latch Flow-table synthesis of a D flip-flop 574 Summary 576 Bibliographic notes 577 Exercises Metastability and synchronization failure Synchronization failure Metastability Probability of entering and leaving an illegal state Demonstration of metastability 585 Summary 589 Bibliographic notes 590 Exercises Synchronizer design Where are synchronizers used? Brute-force synchronizer The problem with multi-bit signals FIFO synchronizer 596 Summary 604 Bibliographic notes 605 Exercises 605 Part VIII Appendix: VHDL coding style and syntax guide Appendix A: VHDL coding style 611 A.1 Basic principles 611 A.2 All state should be in explicitly declared registers 612 A.3 Define combinational design entities so that they are easy to read 614 A.4 Assign all signals under all conditions 615 A.5 Keep design entities small 617 A.6 Large design entities should be structural 617 A.7 Use descriptive signal names 618 A.8 Use symbolic names for subfields of signals 618 A.9 Define constants 618 xiv A.10 Comments should describe intention and give rationale, not state the obvious 619 A.11 Never forget you are defining hardware 620 A.12 Read and be a critic of VHDL code 620 Appendix B: VHDL syntax guide 622 B.1 Comments, identifiers, and keywords 623 B.2 Types 623 B.2.1 Std_logic 624 B.2.2 Boolean 624 B.2.3 Integer 624 B.2.4 Std_logic_vector 625 B.2.5 Subtypes 625 B.2.6 Enumeration 626 B.2.7 Arrays and records 626 B.2.8 Qualified expressions 627 B.3 Libraries, packages, and using multiple files 627 B.4 Design entities 628 B.5 Slices, concatenation, aggregates, operators, and expressions 629 B.6 Concurrent statements 631 B.6.1 Concurrent signal assignment 632 B.6.2 Component instantiation 634 B.7 Multiple signal drivers and resolution functions 636 B.8 Attributes 638 B.9 Process statements 640 B.9.1 The process sensitivity list and execution timing 641 B.9.2 Wait and report statements 644 B.9.3 If statements 644 B.9.4 Case and matching case statements 644 B.9.5 Signal and variable assignment statements 646 B.10 Synthesizable process statements 648 B.10.1 Type 1: purely combinational 649 B.10.2 Type 2: edge-sensitive 649 B.10.3 Type 3: edge-sensitive with asynchronous reset 650 References 653 Index of VHDL design entities 658 Subject index 660
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