LTC4225-1/LTC Dual Ideal Diode and Hot Swap Controller. Applications. Typical Application

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Features n Power Path and Inrush Current Contro for Redundant Suppies n Low Loss Repacement for Power Schottky iodes n Aows Safe Hot Swapping from a Live Backpane n 2.9V to 18V Operating Range n Contros
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Features n Power Path and Inrush Current Contro for Redundant Suppies n Low Loss Repacement for Power Schottky iodes n Aows Safe Hot Swapping from a Live Backpane n 2.9V to 18V Operating Range n Contros N-Channe MOSFETs n Limits Peak Faut Current in 1µs n.5µs Turn-On and Reverse Turn-Off Time n Adjustabe Current Limit with Circuit Breaker n Smooth Switchover without Osciation n Adjustabe Current Limit Faut eay n Faut and Power Status Output n LTC4225-1: Latch Off After Faut n LTC4225-2: Automatic Retry After Faut n 24-Lead 4mm 5mm QFN and SSOP Packages Appications n Redundant Power Suppies n Suppy Hodup n MicroTCA Systems and Servers n Teecom Networks n Power Prioritizer escription LTC4225-1/LTC ua Idea iode and Hot Swap Controer The LTC 4225 offers idea diode and Hot Swap functions for two power rais by controing externa series connected N-channe MOSFETs. MOSFETs acting as idea diodes repace two high power Schottky diodes and the associated heat sinks, saving power and board area. Hot Swap contro MOSFETs aow boards to be safey inserted and removed from a ive backpane by imiting inrush current. The suppy output is aso protected against short-circuit fauts with a fast acting current imit and interna timed circuit breaker. The LTC4225 reguates the forward votage drop across the back-to-back MOSFETs to ensure smooth current transfer from one suppy to the other without osciation. The idea diodes turn on quicky to reduce the oad votage droop during suppy switch-over. If the input suppy fais or is shorted, a fast turn-off minimizes reverse-current transients. The LTC4225 aows independent on/off contro, and reports faut and power good status for the suppy. The LTC features a atch-off circuit breaker, whie the LTC provides automatic retry after a faut. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. Hot Swap is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Typica Appication 137k 2k 2k 137k CPO1 ON1 GN µtca Appication EN2 PWRG2 ON2 FAULT2 CPO2 IN2 SENSE2 GATE2 HGATE2 OUT2.4Ω Si7336AP Si7336AP SENSE1 GATE1 LTC4225 HGATE1 OUT1 FAULT1 PWRG1 EN1 TMR1 TMR2.4Ω Si7336AP Si7336AP 47nF 47nF BACKPLANE PLUG-IN CAR 1 PLUG-IN CAR 2 7.6A 7.6A TA1a POWER ISSIPATION (W) Power issipation vs Load Current IOE (SBG125L) MOSFET (Si7336AP) POWER SAVE LOA CURRENT (A) TA1 1 Absoute Maximum Ratings Suppy Votages, IN2....3V to 24V....3V to 7V Input Votages ON1, ON2, EN1, EN2....3V to 24V TMR1, TMR2...3V to.3v SENSE1, SENSE2....3V to 24V Output Votages FAULT1, FAULT2, PWRG1, PWRG2....3V to 24V CPO1, CPO2 (Note 3)....3V to 35V GATE1, GATE2 (Note 3)....3V to 35V HGATE1, HGATE2 (Note 4)....3V to 35V OUT1, OUT2....3V to 24V (Notes 1, 2) Average Currents FAULT1, FAULT2, PWRG1, PWRG2...5mA...1mA Operating Temperature Range LTC4225C... C to 7 C LTC4225I...4 C to 85 C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec) GN Package...3 C Pin Configuration SENSE1 GN ON IN2 6 SENSE TOP VIEW GATE1 CPO1 HGATE1 OUT1 PWRG GATE2 CPO2 HGATE2 OUT2 PWRG2 19 FAULT1 18 ON1 17 EN1 16 TMR1 15 TMR2 14 EN2 13 FAULT2 UF PACKAGE 24-LEA (4mm 5mm) PLASTIC QFN T JMAX = 125 C, θ JA = 34 C/W EXPOSE PA (PIN 25) PCB GN CONNECTION OPTIONAL CPO1 1 GATE1 2 SENSE1 3 4 ON1 5 6 GN 7 ON2 8 IN2 9 SENSE2 1 GATE2 11 CPO2 12 TOP VIEW 24 HGATE1 23 OUT1 22 PWRG1 21 FAULT1 2 EN1 19 TMR1 18 TMR2 17 EN2 16 FAULT2 15 PWRG2 14 OUT2 13 HGATE2 GN PACKAGE 24-LEA PLASTIC SSOP NARROW T JMAX = 125 C, θ JA = 85 C/W 2 Order Information LEA FREE FINISH TAPE AN REEL PART MARKING* PACKAGE ESCRIPTION TEMPERATURE RANGE LTC4225CUF-1#PBF LTC4225CUF-1#TRPBF Lead (4mm 5mm) Pastic QFN C to 7 C LTC4225CUF-2#PBF LTC4225CUF-2#TRPBF Lead (4mm 5mm) Pastic QFN C to 7 C LTC4225IUF-1#PBF LTC4225IUF-1#TRPBF Lead (4mm 5mm) Pastic QFN 4 C to 85 C LTC4225IUF-2#PBF LTC4225IUF-2#TRPBF Lead (4mm 5mm) Pastic QFN 4 C to 85 C LTC4225CGN-1#PBF LTC4225CGN-1#TRPBF LTC4225GN-1 24-Lead Pastic SSOP C to 7 C LTC4225CGN-2#PBF LTC4225CGN-2#TRPBF LTC4225GN-2 24-Lead Pastic SSOP C to 7 C LTC4225IGN-1#PBF LTC4225IGN-1#TRPBF LTC4225GN-1 24-Lead Pastic SSOP 4 C to 85 C LTC4225IGN-2#PBF LTC4225IGN-2#TRPBF LTC4225GN-2 24-Lead Pastic SSOP 4 C to 85 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V IN =, uness otherwise noted. SYMBOL PARAMETER CONITIONS MIN TYP MAX UNITS Suppies V IN Input Suppy Range V I IN Input Suppy Current ma V IN(UVL) Input Suppy Undervotage Lockout IN Rising V V IN(HYST) Input Suppy Undervotage Lockout mv Hysteresis V INTVCC Interna Reguator Votage V V INTVCC(UVL) Interna V CC Undervotage Lockout Rising V V INTVCC(HYST) Interna V CC Undervotage Lockout Hysteresis mv Idea iode Contro V FW(REG) Forward Reguation Votage mv (V INn V OUTn ) V GATE Externa N-Channe Gate rive (V GATEn V INn ) IN 7V, V FW =.1V, I =, 1µA IN = 7V to 18V, V FW =.1V, I =, 1µA V V I CPO(UP) CPOn Pu-Up Current CPO = IN = 2.9V CPO = IN = 18V I GATE(FPU) GATEn Fast Pu-Up Current V FW =.2V, V GATE = V, CPO = 17V 1.5 A I GATE(FP) GATEn Fast Pu-own Current V FW =.2V, V GATE = 5V 1.5 A t ON(GATE) GATEn Turn-On eay V FW =.2V, C GATE = 1nF.25.5 µs t OFF(GATE) GATEn Turn-Off eay V FW =.2V, C GATE = 1nF.2.5 µs Hot Swap Contro V SENSE(CB) Circuit Breaker Trip Sense Votage mv (V INn V SENSEn ) V SENSE(ACL) Active Current Limit Sense Votage mv (V INn V SENSEn ) V HGATE Externa N-Channe Gate rive (V HGATEn V OUTn ) IN 7V, I =, 1µA IN = 7V to 18V, I =, 1µA V V V HGATE(PG) Gate-Source Votage for Power Good V µa µa 3 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V IN =, uness otherwise noted. SYMBOL PARAMETER CONITIONS MIN TYP MAX UNITS I HGATE(UP) Externa N-Channe Gate Pu-Up Current Gate rive On, HGATE = V µa I HGATE(N) Externa N-Channe Gate Pu-own Gate rive Off, OUT =, µa Current HGATE = OUT 5V I HGATE(FP) t PHL(SENSE) t OFF(HGATE) t (HGATE) Externa N-Channe Gate Fast Pu-own Current Sense Votage (INn SENSEn) High to HGATEn Low ENn High to HGATEn Low ONn Low to HGATEn Low INn Low to HGATEn Low ONn High, ENn Low to HGATEn Turn-On eay Fast Turn-Off, OUT =, ma HGATE = OUT 5V V SENSE = 3mV, C HGATE = 1nF.5 1 µs µs µs µs ms t P(HGATE) ONn to HGATEn Propagation eay ON = Step.8V to 2V 1 2 µs Input/Output Pin I SENSE SENSEn Input Current SENSE = µa V ON(TH) ONn Threshod Votage ON Rising V V ON(HYST) ONn Hysteresis mv V ON(RESET) ONn Faut Reset Threshod Votage ON Faing V I ON(LEAK) ONn Input Leakage Current ON = 5V ±1 µa V EN(TH) ENn Threshod Votage EN Rising V V EN(HYST) ENn Hysteresis mv I EN(UP) ENn Pu-Up Current EN = 1V µa V TMR(TH) TMRn Threshod Votage TMR Rising TMR Faing I TMR(UP) TMRn Pu-Up Current TMR = 1V, In Faut Mode µa I TMR(N) TMRn Pu-own Current TMR = 2V, No Fauts µa I TMR(RATIO) TMRn Current Ratio I TMR(N) /I TMR(UP) % I OUT OUTn Current OUT = 11V, IN =, ON = 2V OUT = 13V, IN =, ON = 2V V OL Output Low Votage (FAULTn, PWRGn) I = 1mA.15.4 V V OH Output High Votage (FAULTn, PWRGn) I = 1µA 1.5 V I OH Input Leakage Current (FAULTn, PWRGn) V = 18V ±1 µa I PU Output Pu-Up Current V = 1.5V µa (FAULTn, PWRGn) t RST(ON) ONn Low to FAULTn High 2 4 µs V V µa ma Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A currents into device pins are positive; a currents out of the device pins are negative. A votages are referenced to GN uness otherwise specified. Note 3: An interna camp imits the GATE and CPO pins to a minimum of 1V above and a diode beow IN. riving these pins to votages beyond the camp may damage the device. Note 4: An interna camp imits the HGATE pin to a minimum of 1V above and a diode beow OUT. riving this pin to votages beyond the camp may damage the device. 4 Typica Performance Characteristics LTC4225-1/LTC T A = 25 C, V IN =, uness otherwise noted. I IN (ma) IN Suppy Current vs Votage Load Reguation CPO Votage vs Current (V) 6 V IN = V IN = 3.3V 2 1 V CPO V IN ( V CPO ) (V) V IN = 18V 6 4 V IN = 2.9V V IN (V) I LOA (ma) I CPO (µa) G G G3 V GATE V IN ( V GATE ) (V) iode Gate Votage vs Current Hot Swap Gate Votage vs Current OUT Current vs Votage V OUT = V IN.1V V IN = 18V V IN = 2.9V GATE RIVE ( V HGATE ) (V) 14 V OUT = V IN 12 V IN = V IN = 2.9V 4 2 I OUT (ma) 2.5 V IN = I GATE (µa) I HGATE (µa) V OUT (V) G G G6 CIRCUIT BREAKER TRIP VOLTAGE (mv) Circuit Breaker Trip Votage vs Temperature TEMPERATURE ( C) G7 ACTIVE CURRENT LIMIT SENSE VOLTAGE (mv) Active Current Limit Sense Votage vs Temperature TEMPERATURE ( C) G8 ACTIVE CURRENT LIMIT ELAY (µs) Active Current Limit eay vs Sense Votage C HGATE = 1nF SENSE VOLTAGE (V IN V SENSE ) (mv) G9 5 Typica Performance Characteristics T A = 25 C, V IN =, uness otherwise noted. 11. HGATE Pu-Up Current vs Temperature 13 TMR Pu-Up Current vs Temperature.8 PWRG, FAULT Output Low Votage vs Current HGATE PULL-UP CURRENT (µa) TMR PULL-UP CURRENT (µa) OUTPUT LOW VOLTAGE (V) TEMPERATURE ( C) TEMPERATURE ( C) CURRENT (ma) G G G12 Pin Functions CPO1, CPO2: Charge Pump Output. Connect a capacitor from CPO1 or CPO2 to the corresponding or IN2 pin. The vaue of this capacitor is approximatey 1 the gate capacitance (C ISS ) of the externa MOSFET for idea diode contro. The charge stored on this capacitor is used to pu up the gate during a fast turn-on. Leave this pin open if fast turn-on is not needed. GATE1, GATE2: Idea iode MOSFET Gate rive Output. Connect this pin to the gate of an externa N-channe MOSFET for idea diode contro. An interna camp imits the gate votage to above and a diode votage beow IN. uring fast turn-on, a 1.5A pu-up charges GATE from CPO. uring fast turn-off, a 1.5A pu-down discharges GATE to IN. EN1, EN2: Enabe Input. Ground this pin to enabe Hot Swap contro. If this pin is pued high, the MOSFET is not aowed to turn on. A 1µA current source pus this pin up to a diode beow. Upon EN going ow when ON is high, an interna timer provides a 1ms start-up deay for debounce, after which the faut is ceared. Exposed Pad (UF Package): The exposed pad may be eft open or connected to device ground. FAULT1, FAULT2: Faut Status Output. Open-drain output that is normay pued high by a 1µA current source to a diode beow. It may be pued above using an externa pu-up. It pus ow when the circuit breaker is tripped after an overcurrent faut timeout. Leave open if unused. GN: evice Ground. HGATE1, HGATE2: Hot Swap MOSFET Gate rive Output. Connect this pin to the gate of the externa N-channe MOSFET for Hot Swap contro. An interna 1µA current source charges the MOSFET gate. An interna camp imits the gate votage to above and a diode beow OUT. uring turn-off, a 3µA pu-down discharges HGATE to ground. uring an output short or undervotage ockout, a fast 2mA pu-down discharges HGATE to OUT., IN2: Positive Suppy Input and MOSFET Gate rive Return. The 5V suppy is generated from and IN2 via an interna diode-or. The votage sensed at this pin is used to contro GATE for forward votage reguation and reverse turn-off. It aso senses the positive side of the current sense resistor. The gate fast pu-down current returns through this pin when GATE is discharged. 6 Pin Functions : Interna 5V Suppy ecouping Output. This pin must have a or arger capacitor. An externa oad of ess than 5µA can be connected at this pin. ON1, ON2: On Contro Input. A rising edge above 1.235V turns on the externa Hot Swap MOSFET and a faing edge beow 1.155V turns it off. Connect this pin to an externa resistive divider from IN to monitor the suppy undervotage condition. Puing the ON pin beow.6v resets the eectronic circuit breaker. OUT1, OUT2: Output Votage Sense and MOSFET Gate rive Return. Connect this pin to the output side of the externa MOSFET. The votage sensed at this pin is used to contro GATE. The gate fast pu-down current returns through this pin when HGATE is discharged. PWRG1, PWRG2: Power Status Output. Open-drain output that is normay pued high by a 1µA current source to a diode beow. It may be pued above using an externa pu-up. It pus ow when the LTC4225-1/LTC MOSFET gate drive between HGATE and OUT exceeds the gate-to-source votage of 4.2V. Leave open if unused. SENSE1, SENSE2: Negative Current Sense Input. Connect this pin to the output of the current sense resistor. The current imit circuit contros HGATE to imit the votage between IN and SENSE to 65mV. A circuit breaker trips when the sense votage exceeds 5mV for more than a faut fiter deay configured at the TMR pin. TMR1, TMR2: Timer Capacitor Termina. Connect a capacitor between this pin and ground to set a 12ms/µF duration for current imit before the externa Hot Swap MOSFET is turned off. The duration of the off time is 617ms/µF, resuting in a 2% duty cyce. 7 LTC4225-1/LTC Bock iagram HGATE1 A1 SENSE1 SENSE2 IN2 65mV 5mV 5mV 65mV ECB1 ECB2 A2 HGATE2 1µA 1µA CPO1 1µA CHARGE PUMP 1 CHARGE PUMP 2 1µA CPO2 GATE1 OUT1 GATE RIVER 1 GA1 25mV 2.2V 5V LO 25mV GA2 GATE RIVER 2 GATE2 OUT2 UV3 1.9V UV1 UV2 IN2 1.9V ON1 1µA 1.235V.6V CP1 CP2 HGATE1 ON FAULT1 RESET HGATE2 ON FAULT2 RESET CP3 CP V ON2.6V 1µA EN V CP5 CAR1 PRESENCE ETECT CAR2 PRESENCE ETECT CP V EN2 TMR1 1µA 1.235V.2V 2µA CP7 CP8 LOGIC CP9 CP V.2V 1µA 2µA TMR2 1µA 1µA 1µA 1µA FAULT1 FAULT2 PWRG1 GN PWRG2 EXPOSE PA* *UF PACKAGE ONLY B 8 Operation The LTC4225 functions as an idea diode with inrush current imiting and overcurrent protection by controing two externa back-to-back N-channe MOSFETs (M and M H ) on a suppy path. This aows boards to be safey inserted and removed in systems with a backpane powered by redundant suppies, such as µtca appications. The LTC4225 has two separate idea diode and Hot Swap controers, each providing independent contro for the two input suppies. When the LTC4225 is first powered up, the gates of the back-to-back MOSFETs are hed ow, keeping them off. The gate drive ampifier (GA1, GA2) monitors the votage between the IN and OUT pins and drives the GATE pin. The ampifier quicky pus up the GATE pin, turning on the MOSFET for idea diode contro, when it senses a arge forward votage drop. The stored charge in an externa capacitor connected between the CPO and IN pins provides the charge needed to quicky turn on the idea diode MOSFET. An interna charge pump charges up this capacitor at device power-up. The GATE pin sources current from the CPO pin and sinks current into the IN and GN pins. Puing the ON pin high and the EN pin ow initiates a 1ms debounce timing cyce. After this timing cyce, a 1µA current source from the charge pump ramps up the HGATE pin. When the Hot Swap MOSFET turns on, the inrush current is imited at a eve set by an externa sense resistor (R S ) connected between the IN and SENSE pins. An active current imit ampifier (A1, A2) servos the gate of the MOSFET to 65mV across the current sense resistor. Inrush current can be further reduced, if desired, by adding a capacitor from HGATE to GN. When the MOSFET s gate overdrive (HGATE to OUT votage) exceeds 4.2V, the PWRG pin pus ow. LTC4225-1/LTC When both of the MOSFETs are turned on, the gate drive ampifier contros GATE to servo the forward votage drop (V IN V OUT ) across the sense resistor and the back-to-back MOSFETs to 25mV. If the oad current causes more than 25mV of votage drop, the gate votage rises to enhance the MOSFET used for idea diode contro. For arge output currents, the MOSFET s gate is driven fuy on and the votage drop across the MOSFETs is equa to the sum of the I LOA R S(ON) of the two MOSFETs in series. In the case of an input suppy short circuit when the MOSFETs are conducting, a arge reverse current starts fowing from the oad towards the input. The gate drive ampifier detects this faiure condition as soon as it appears and turns off the idea diode MOSFET by puing down the GATE pin. In the case where an overcurrent faut occurs on the suppy output, the current is imited to 65mV/R S. After a faut fiter deay set by 1µA charging the TMR pin capacitor, the circuit breaker trips and pus the HGATE pin ow, turning off the Hot Swap MOSFET. Ony the suppy at faut is affected, with the corresponding FAULT pin atched ow. At this point, the GATE pin continues to pu high and keeps the idea diode MOSFET on. Interna camps imit both the GATE to IN and CPO to IN votages to. The same camp aso imits the CPO and GATE pins to a diode votage beow the IN pin. Another interna camp imits the HGATE to OUT votage to and aso camps the HGATE pin to a diode votage beow the OUT pin. Power to the LTC4225 is suppied from either the IN or OUT pins, through an interna diode-or circuit to a ow dropout reguator (LO). That LO generates a 5V suppy at the pin and powers the LTC4225 s interna ow votage circuitry. 9 Appications Information High avaiabiity systems often empoy parae-connected power suppies or battery feeds to achieve redundancy and enhance system reiabiity. Power ORing diodes are commony used to connect these suppies at the point of oad, but at the expense of power oss due to significant diode forward votage drop. The LTC4225 minimizes this power oss by using externa N-channe MOSFETs for the pass eements, aowing for a ow votage drop from the suppy to the oad when the MOSFETs are turned on. When an input source votage drops beow the output common suppy votage, the appropriate MOSFET is turned off, thereby matching the function and performance of an idea diode. By adding a current sense resistor and configuring two MOSFETs back-to-back with separate gate contro, the LTC4225 enhances the idea diode performance with inrush current imiting and overcurrent protection (see Figure 1). This aows the boards to be safey inserted and removed from a ive backpane without damaging the connector. Interna V CC Suppy The LTC4225 can operate with input suppies from 2.9V to 18V at the IN pins. The power suppy to the device is internay reguated at 5V by a ow dropout reguator (LO) with an output at the pin. An interna diode-or circuit seects the highest of the suppies at the IN and OUT pins to power the device through the LO. The diode-or scheme permits the device s power to be temporariy kept aive by the OUT oad capacitance when the IN suppies have coapsed or shut off. An undervotage ockout circuit prevents a of the MOSFETs from turning on unti the votage exceeds 2.2V. A capacitor is recommended between the and GN pins, cose to the device for bypassing. No externa suppy shoud be connected at the pin so as not to affect the LO s operation. A sma externa oad of ess than 5µA can be connected at the pin. Turn-On Sequence The board power suppy at the OUT pin is controed with two externa back-to-back N-channe MOSFETs (M, M H ). The MOSFET M on the suppy side functions as an idea diode, whie M H on the oad side acts as a Hot Swap controing the power suppied to the output oad. The sense resistor, R S, monitors the oad current for overcurrent detection. The HGATE capacitor, C HG, contros the gate sew rate to imit the inrush current. Resistor R HG with C HG compensates the current contro oop, whie R H prevents high frequency osciations in the Hot Swap MOSFET. V R2 137k R1 2k R3 2k R4 137k C F1 1nF C F2 1nF BULK SUPPLY BYPASS CAPACITOR C1 CPO1 ON1 GN C CP1 R S1.4Ω M 1 Si7336AP SENSE1 GATE1 LTC4225 M H1 Si7336AP R H1 1Ω HGATE1 R HG1 47Ω C HG1 15nF OUT1 FAULT1 PWRG1 EN1 TMR1 TMR2 EN2 PWRG2 ON2 FAULT2 CPO2 IN2 SENSE2 GATE2 HGATE2 OUT2 R5 1k C T2 47nF R7 1k V R6 1k R8 1k C T1 47nF PLUG-IN CAR 1 PLUG-IN CAR 2 7.6A C L1 16µF V IN2 BULK SUPPLY BYPASS CAPACITOR C C
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