EE141- Spring 2003 Lecture 23. Timing and Clocks EE141. Announcements. Hardware lab this week Project-2 will be launched next week EE141 - PDF

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- Spring 2003 Lecture 23 Timing and Clocks Announcements Hardware lab this week Project-2 will be launched next week Today s Lecture Sequential Circuits (Cont.) Timing Sequential Logic Sequential Circuits
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- Spring 2003 Lecture 23 Timing and Clocks Announcements Hardware lab this week Project-2 will be launched next week Today s Lecture Sequential Circuits (Cont.) Timing Sequential Logic Sequential Circuits (Cont.) Schmitt Trigger Monostable Multivibrators Astable Multivibrators Schmitt Trigger In Out V ou t V OH VTC with hysteresis V OL Restores signal slopes V M V M+ V in Noise Suppression using a Schmitt Trigger V in V out V M+ V M t 0 t t 0 +t p t CMOS Schmitt Trigger V DD M 2 M 4 V in X V out M 1 M 3 Moves switching threshold of the first inverter (V) V X (V) V x Schmitt Trigger Simulated VTC V M V M k= 1 k= 2 k= 3 k= V in (V) Voltage-transfer characteristics with hysteresis V in (V) The effect of varying the width of the PMOS device M 4. W(M 4 ) = k*0.5µm CMOS Schmitt Trigger (2) V DD M 4 M 3 M 6 In Out M 2 X M 5 V DD M 1 Multivibrator Circuits R S Bistable Multivibrator flip-flop, Schmitt Trigger T Monostable Multivibrator one-shot Astable Multivibrator oscillator Transition-Triggered Monostable In DELAY t d Out t d Delay element controls the duration of the pulse. Monostable Trigger (RC-based) V DD In A C R B Out Trigger circuit In B V M Waveforms Out t t 1 t 2 Astable Multivibrators (Oscillators) N-1 Volts Ring Oscillator 3.0 V 1 V 3 V time (ns) simulated response of a 5-stage oscillator Voltage Controlled Oscillator (VCO) V DD M6 V DD M4 Schmitt Trigger restores signal slopes In M2 I ref M1 I ref V contr M5 M3 Current starved inverter 6 t ph L (nsec) V contr (V) propagation delay as a function of control voltage Timing Outline Timing parameters Clock nonidealities (skew and jitter) Impact of skew on timing Impact of jitter on timing Flip-flop- vs. Latch-based timing Clock distribution Datapath and Timing Parameters In R1 D Q Combinational Logic R2 D Q CLK t CLK1 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd R1 and R2 can be latches or flip-flops Latch Parameters D Q D PW m T H T SU Q T -Q T D-Q Delays can be different for rising and falling data transitions Flip-Flop Parameters D Q D PW m T H T SU Q T -Q Delays can be different for rising and falling data transitions Timing Constraints (Cycle Time and Race Margin) In R1 D Q Combinational Logic R2 D Q CLK t CLK1 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd Cycle time: T t c-q + t logic + t su Race margin: t hold t c-q,cd + t logic,cd Outline Timing parameters Clock nonidealities (skew and jitter) Impact of skew on timing Impact of jitter on timing Flip-flop- vs. Latch-based timing Clock distribution Clock skew Clock Nonidealities» Spatial variation in temporally equivalent clock edges; deterministic + random, t SK Clock jitter» Temporal variations in consecutive edges of the clock signal; modulation + random noise» Cycle-to-cycle (short-term) t JS» Long term t JL Variation of the pulse width» for level sensitive clocking Clock Skew and Jitter t SK t JS Both skew and jitter affect the effective cycle time Only skew affects the race margin Clock Skew # of registers Earliest occurrence of edge Nominal T sk /2 Latest occurrence of edge Nominal + T sk /2 Insertion delay T sk delay Max skew Sources of Skew and Jitter Devices 2 4 Power Supply 3 Interconnect 6 Capacitive Load 1 Clock Generation 5 Temperature 7 Coupling to Adjacent Lines Positive Skew T CLK + δ CLK1 1 δ T CLK 3 CLK2 2 4 δ + t h Launching edge arrives before the receiving edge Negative Skew T CLK + δ CLK1 1 T CLK 3 CLK2 2 δ 4 Receiving edge arrives before the launching edge Positive and Negative Skew In R1 D Q Combinational Logic R2 D Q Combinational Logic R3 D Q CLK t CLK1 t CLK2 t CLK3 delay delay (a) Positive skew In R1 D Q Combinational Logic R2 D Q Combinational Logic R3 D Q t CLK1 t CLK2 t CLK3 delay delay CLK (b) Negative skew Outline Timing parameters Clock nonidealities (skew and jitter) Impact of skew on timing Impact of jitter on timing Flip-flop- vs. Latch-based timing Clock distribution Timing Constraints In R1 D Q Combinational Logic R2 D Q CLK t CLK1 t CLK2 t c q t c q, cd t su, t hold t logic t logic, cd Cycle time: T t c-q + t logic + t su Race margin: t hold t c-q,cd + t logic,cd Impact of Clock Skew on Timing: Cycle Time (Long Path) δ t c-q t logic t su T Arrival of next cycle t c-q + t logic + t su T + δ T t c-q + t logic + t su - δ Impact of Clock Skew on Timing: Race Margin (Short Path) t c-q,cd t logic,cd t hold δ Data must not arrive before this time t c-q,cd + t logic,cd t hold + δ t hold + δ t c-q,cd + t logic,cd Impact of Clock Skew on Timing Positive skew improves performance T t c-q + t logic + t su - δ Negative skew improves race margin t hold + δ t c-q,cd + t logic,cd Worst-case δ really matters How to counter Clock Skew? Negative Skew REG φ REG. REG log Out In REG φ φ Positive Skew φ Clock Distribution Outline Timing parameters Clock nonidealities (skew and jitter) Impact of skew on timing Impact of jitter on timing Flip-flop- vs. Latch-based timing Clock distribution Impact of Clock Jitter 2 T CLK 5 CLK t ji tte r t jitter 6 In REGS CLK t c-q, t c-q, cd t su, t hold t jitter Combinational Logi c t logic t logic, cd Impact of Clock Jitter on Timing: Cycle Time (Late-Early Problem) t jitter t c-q t logic t su T Latest point of launching Earliest arrival of next cycle t c-q + t logic + t su T t jitter t jitter T t c-q + t logic + t su + 2 t jitter Impact of Clock Jitter on Timing Negative impact on cycle time T t c-q + t logic + t su + 2 t jitter No direct effect on race immunity (same edge) Jitter reduces performance Combined Impact of Clock Jitter and Skew Impact of Clock Skew and Jitter: Cycle Time (Late-Early Problem) t jitter + δ t c-q t logic t su T Latest point of launching Earliest arrival of next cycle t c-q + t logic + t su T t jitter t jitter + δ T t c-q + t logic + t su - δ + 2 t jitter Impact of Clock Skew and Jitter: Race Margin (Early-Late Problem) Earliest point of launching t c-q,cd t logic,cd Latest arrival of next cycle t jitter + δ t hold Nominal clock edge Data must not arrive before this time t c-q,cd + t logic,cd t jitter t hold + t jitter + δ t hold + 2 t jitter + δ t c-q,cd + t logic,cd Combined Impact of Clock Skew and Jitter on Timing Cycle time T t c-q + t logic + t su - δ + 2 t jitter» Positive skew improves performance» Negative skew reduces performance» Jitter reduces performance Race t hold + 2 t jitter + δ t c-q,cd + t logic,cd» Skew reduces race margin» Jitter reduces acceptable skew Outline Timing parameters Clock nonidealities (skew and jitter) Impact of skew on timing Impact of jitter on timing Flip-flop- vs. Latch-based timing Clock distribution Flip-Flop Based Timing φ Logic delay Skew Flip-flop delay Flip -flop Logic T SU φ = 0 T -Q φ = 1 [Horowitz96] Flip-Flops and Dynamic Logic Logic delay T SU T SU T -Q φ = 0 T -Q φ = 1 φ = 0 φ = 1 Precharge Evaluate Logic delay Evaluate Precharge Flip-flops are used only with static logic Latch Timing t D-Q D Q When data arrives to transparent latch Latch is a soft barrier t -Q When data arrives to closed latch Data has to be re-launched Latch Timing (Cont.) D Q D PW m T H T SU Q T -Q T D-Q Single-Phase Clock with Latches φ Latch [Unger and Tan Trans. on Comp. 10/86] Logic T skl T skl T skt T skt PW P Latch-Based Design L1 latch is transparent when φ = 1 φ L2 latch is transparent when φ = 0 L1 Latch Logic L2 Latch Logic Latch-Based Timing φ Static logic Skew L1 Latch Logic L2 Latch φ = 1 L2 latch L1 latch Logic Long path φ = 0 Can tolerate skew! Short path Outline Timing parameters Clock nonidealities (skew and jitter) Impact of skew on timing Impact of jitter on timing Flip-flop- vs. Latch-based timing Clock distribution Clock Distribution CLOCK H-Tree Network Observe: Only Relative Skew is Important More realistic H-tree [Restle98] Clock Network with Distributed Buffering Local Area Module Module secondary clock drivers Module Module Module Module main clock driver CLOCK Reduces absolute delay, and makes Power-Down easier Sensitive to variations in Buffer Delay The Grid System Driver GCLK GCLK Driver Driver GCLK No rc-matching Large power Driver GCLK Example: DEC Alpha Clock Frequency: 300 MHz Million Transistors Total Clock Load: 3.75 nf Power in Clock Distribution network : 20 W (out of 50) Uses Two Level Clock Distribution: Single 6-stage driver at center of chip Secondary buffers drive left and right side clock grid in Metal3 and Metal4 Total driver size: 58 cm! Clocking t cycle = 3.3ns 2 phase single wire clock, t rise = 0.35ns final drivers t skew = 150ps distributed globally 2 distributed driver channels» Reduced RC delay/skew» Improved thermal distribution» 3.75nF clock load» 58 cm final driver width Local inverters for latching Clock waveform pre-driver Location of clock driver on die Conditional clocks in caches to reduce power More complex race checking Device variation Clock Drivers Clock Skew in Alpha Processor EV6 (Alpha 21264) Clocking 600 MHz 0.35 micron CMOS t cycle = 1.67ns t rise = 0.35ns Global clock waveform t skew = 50ps PLL 2 Phase, with multiple conditional buffered clocks» 2.8 nf clock load» 40 cm final driver width Local clocks can be gated off to save power Reduced load/skew Reduced thermal issues Multiple clocks complicate race checking Clocking EV6 Clock Results ps GCLK Skew (at Vdd/2 Crossings) ps GCLK Rise Times (20% to 80% Extrapolated to 0% to 100%) EV7 Clock Hierarchy Active Skew Management and Multiple Clock Domains NCLK (Mem Ctrl) + widely dispersed drivers DLL DLL DLL + DLLs compensate static and lowfrequency variation + divides design and verification effort L2L_CLK (L2 Cache) GCLK (CPU Core) PLL L2R_CLK (L2 Cache) - DLL design and verification is added work SYSCLK + tailored clocks
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