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DESIGN OF RF FRONT-END CIRCUIT BLOCKS FOR LOW-POWER APPLICATIONS LIM KOK MENG School of Electrical and Electronic Engineering A thesis submitted to the Nanyang Technological University in partial fulfillment
DESIGN OF RF FRONT-END CIRCUIT BLOCKS FOR LOW-POWER APPLICATIONS LIM KOK MENG School of Electrical and Electronic Engineering A thesis submitted to the Nanyang Technological University in partial fulfillment of the requirement for the degree of Master of Engineering 2008 STATEMENT OF ORIGINALITY I hereby certify the content of this thesis is the result of work done by me and has not been submitted for higher degree to any other University or Institution. Date Lim Kok Meng ACKNOWLEDGMENTS With a deep sense of gratitude, I wish to express my sincere thanks to my supervisor, Professor Yeo Kiat Seng, for his continuous insight, enthusiasm and encouragement. His deep passion for various scientific problems has taught me a lot. His guidance during the development of my research has been invaluable. I also would like to thank Professor Do Manh Anh. His professional attitude, continuous support and management skill deserve special acknowledgment. People at Centre for Integrated Circuits and Systems have contributed to this work. I had the most wonderful learning experience working with a team of very active and bright engineers in the RFIC design field, which include Sia Choon Beng, Dr. Ng Choon Yong, Ong Beng Hwee and Yang Wei. It would have been impossible to achieve these research results without the consistent technical support of Mr. Richard, Miss Guee, Mr Lim Wei Meng and Mrs. Min Lin in IC Design Lab II. Finally, I will never find the words to express the gratitude that I owe to my family. I TABLE OF CONTENTS ACKNOWLEDGMENTS...I TABLE OF CONTENTS... II SUMMARY...IV LIST OF FIGURES...VI LIST OF TABLES... VIII CHAPTER 1 INTRODUCTION MOTIVATION OBJECTIVES MAJOR CONTRIBUTIONS OF THE THESIS ORGANIZATION OF THE THESIS...4 CHAPTER 2 TECHNOLOGY REVIEW BIPLOAR JUNCTION TRANSISTORS LARGE SIGNAL MODEL SMALL SIGNAL MODEL FREQUENCY RESPONSE NOISE SOURCES METAL OXIDE SEMICONDUCTOR TRANSISTOR LARGE SIGNAL MODEL SMALL SIGNAL MODEL FREQUENCY RESPONSE NOISE SOURCES PASSIVE COMPONENTS INDUCTORS CAPACITORS CONCLUSION...24 CHAPTER 3 RF CIRCUIT PERFORMANCE PARAMETERS SYSTEM ANALYSIS SENSITIVITY NOISE FIGURE...26 II 3.1.3 GAIN COMPRESSION THIRD ORDER INTERCEPT DYNAMIC RANGE SYSTEM ARCHITECTURE SUPERHETERODYNE DIRECT CONVERSION LOW IF CONCLUSION...34 CHAPTER 4 DESIGN OF WEAK INVERSION LNA DESIGN CONSIDERATIONS TRANSISTOR SELECTION DESIGN FOR TESTING RESULTS CONCLUSION...53 CHAPTER 5 DESIGN OF OVER COAX TRANSMITTER DESIGN SPECIFICATIONS TRANSMITTER ARCHITECTURE BIASING CIRCUIT MIXERS BUFFERS PRE-AMPLIFIERS FABRICATION & RESULTS LAYOUT & PACKAGING LOSS MECHANISM RESULTS CONCLUSION...78 CHAPTER 6 CONCLUSION & FUTURE WORK CONCLUSION FUTURE WORK...80 REFERENCES...82 APPENDIX A...86 APPENDIX B...95 III SUMMARY This report aims to provide a comprehensive review as well as the design of the various high frequency circuits found in almost all the transceivers in the market today. Wireless communication has become a natural part of everyone s life, its presence can be seen all around. The high frequency circuits include low noise amplifiers (LNA), mixers and pre-amplifiers (PA). In every receiver system, the LNA is the first block placed in the receive path, therefore its performance is critical in the exact operation of the receiver. The primary role of the LNA is to amplify the weak Radio Frequency (RF) signals, having suffered propagation loss after transmission through a medium, while minimizing its noise contribution to the overall system. Gain and noise figure are well correlated, higher gain would produce lower noise figure. Correspondingly, to achieve high gain, power consumption is increased. For mobile wireless devices, this would cause a severe drain on battery life. Therefore a novel LNA, operating in the subthreshold region is introduced to alleviate this issue. Most modulators and demodulators are not able to achieve the high sampling rate required at RF frequencies. Thus, mixers circuits are needed to convert the modulated signals with a carrier frequency to the desired frequency. In the case of a transmitter system, the mixer is used to up convert the modulated immediate frequency (IF) into RF signal for transmission. Due to modulation scheme adopted and high bandwidth requirements of certain wireless applications, a wideband and high linearity mixer is needed to fulfill these functions. Lastly, a transmitter would need to drive an off chip load, usually in the form of an antenna. A PA is usually employed to accomplish the task. By incorporating a power amplifier on-chip several considerations need to be addressed, a power amplifier have high gain resulting in a huge signal swings. These signals tend to find their way to other frequency sensitive circuits such as oscillators, through certain feedback paths or substrate coupling. This effect is normally known as IV injection pulling. Proper shielding or isolation is therefore crucial for the proper operation of the entire transceiver system. V LIST OF FIGURES Figure 2-1: Cross sectional view of an NPN BJT...7 Figure 2-2 : Symbol and sign conventions for (a) NPN transistor; (b) PNP transistor...7 Figure 2-3 : IC versus VCE...9 Figure 2-4 : BJT Small Signal Model...10 Figure 2-5 : Small Signal Model for Calculation of f T...11 Figure 2-6 : Noise Sources of BJT...12 Figure 2-7 : Cross Sectional View of Typical NMOS Transistor...13 Figure 2-8 : Small Signal Model of MOS Transistors...15 Figure 2-9 : Small Signal Model with Parasitic Capacitance...16 Figure 2-10 : Small Signal Model of MOS Transistor with Noise Sources...17 Figure 2-11 : a)square b)octagonal c)hexagenal d)circular layout pattern...18 Figure 2-12 : The lump element model of an on-chip inductor...19 Figure 2-13 : Simulation Setup...20 Figure 2-14 : Graphical Representation of Inductor s Parameters...22 Figure 2-15 : a)mim Capacitor b)equivalent Model...22 Figure 2-16 : Simulation Results of MIM Capacitors...24 Figure 3-1 : Impact of the noise figure as it moves down the chain a) High Power Incoming Signal b) Low Power Incoming Signal...28 Figure 3-2 : P1dB Compression Point...29 Figure 3-3 : Graphical Representation of IP3 Concept...30 Figure 3-4 : Superheterodyne Architecture...32 Figure 3-5 : Direct Conversion System...33 Figure 3-6 : Low IF Architecture...34 Figure 4-1 : A Simple Push-Pull Amplifier...36 Figure 4-2 : Push-Pull Amplifier showing Cross-over Distortion...37 Figure 4-3 : Schematic of Proposed LNA...38 Figure 4-4 : Small Signal Analysis of the Push Pull Amplifier with Load...39 Figure 4-5 : Length 0.18um Width 200um a) Small Signal Gain b) Noise Figure c) Linearity d) gm/id...88 Figure 4-6 : Equipment Testbench...44 Figure 4-7 : Input Impedance of Core LNA...45 Figure 4-8 : Cascoded Inductor Source Degeneration LNA...46 Figure 4-9 : Small Signal Analysis...46 Figure 4-10 : T-Coil Load Output Matching...48 Figure 4-11 : Layout of Proposed LNA...49 Figure 4-12 : S11 Input Matching...49 VI Figure 4-13 : S22 Output Matching...50 Figure 4-14 : S21 Power Gain...50 Figure 4-15 : Noise Figure...51 Figure 4-16 : P1dB Compression Curve...52 Figure 4-17 : IIP 3 Curves...52 Figure 5-1 : Hybrid IEEE over Coax System...55 Figure 5-2 : Block Diagram for the Transmitter...58 Figure 5-3 : NTAT Current...59 Figure 5-4 : Pseudo-Differential Mixer...61 Figure 5-5 : Differential Common Collector Buffer...62 Figure 5-6 : a) Envelop Modulation b) Non-constant Envelop Modulation c) Spectral Regrowth..63 Figure 5-7 : Differential Class A PA...64 Figure 5-8 : Double Down Bond...65 Figure 5-9 : QFN Lead Frame...66 Figure 5-10 : Package Model...67 Figure 5-11: Microphotograph of the Transmitter...67 Figure 5-12 : Custom Built Evaluation Board...68 Figure 5-13 : Cable Loss Calibrated at 1.0 GHz...69 Figure 5-14 : Cable Loss Calibrated at 2.4 GHz...69 Figure 5-15 : Loss Measured from SMA Connector, 15 cm PCB 50 Ω Transmission Trace & Balun 1.0 GHz...70 Figure 5-16 : Loss Measured from SMA Connector, 15 cm PCB 50 Ω Transmission Trace & Balun 2.4 GHz...70 Figure 5-17 : S-parameter S Figure 5-18 : S-parameter S Figure 5-19 : a) Input Signal Power set at dbm b) Measured Output Signal Power -5.4 dbm73 Figure 5-20 : Spurs Rejection between 50.0MHz to 1.5GHz...73 Figure 5-21 : LO Leakage and High Frequency Spurs...74 Figure 5-22 : OIP3 Measurement Result a) Two Tone Input Signal Injected b) Two Tone Output Signal Measured c) Calculation of IP Figure 5-23 : Gain Variation of Varactor Bank Switching...76 VII LIST OF TABLES Table 2-1 : Calculation using Y-parameters...20 Table 4-1 : Performance comparisons of this work and recently reported 2.4 GHz 0.18 µm CMOS LNAs...53 Table 5-1 : Transmitter Design Specifications...57 Table 5-2 : Packaging Materials Parameters and Properties...66 Table 5-3 : Specification versus Measured Results...77 Table 5-4 : Performance Comparisons...77 Table 5-5 : Performance Comparison...77 VIII CHAPTER 1 INTRODUCTION 1.1 MOTIVATION Mobile wireless communication applications are fast becoming a part of our daily lives. Their global market potential has been the continuous driving force for the improvements in the performance of these products, for example, better coverage, higher data rate, longer battery life, smaller size, and also lower cost. To meet these goals, researchers are focusing on implementing a single chip transceiver in the standard complementary metal oxide semiconductor (CMOS) or silicon germanium (SIGE) technology. The single chip solution will have both the digital signal processing circuits and the radio frequency front-end all integrated on the same chip. There is a wide range of applications specific RF chips. It is not possible to design a RF chip to cater for all the different applications. Furthermore, with the ever growing popularity of system-on-chip (SOC), radio frequency (RF) integrated circuit is facing more and more challenges to meet the demands of various wireless applications. To contain the scope of the effort, we have focus on two main challenges. The first challenge is faced by mobile wireless communication devices. As stated, more and more companies are focusing on SOC solutions for their products. The mobile wireless communication applications based on silicon technologies can largely increase the integration density of RF module, base-band and digital signal processing (DSP) modules, etc. Therefore, with so many different power hungry modules packed into a single device, the battery life is placed under sever strain. There are many widely used frequency range of personal mobile wireless communication applications just lying in low gigahertz range, such as 900 MHz of global system for mobile communication (GSM) system, 1.8 GHz of digital communication system (DCS) system and 2.4 GHz for both Bluetooth technology 1 and IEEE b/g [1] standard. As a result for such demand for mobility, to extend the battery life, low power circuits are becoming more and more popular. To circumvent this problem, at the circuit level, the use of CMOS technology calls for a re-thinking of the traditional RF design method that relies heavily on the operation of MOS transistors in the saturation region which translates to a higher current consumption, to achieve targeted specifications. The first portion of this research focused primarily on the design of a fully-integrated weak inversion LNA using CMOS technology. In the receive path, the first block encountered is the LNA, performance of this block is therefore critical to ensure proper operation of the receiver. Its goal is to provide gain to the weak RF signals received with minimum noise contribution. Both specifications are being met with the MOS transistors biased in the saturation region. Unlike traditional LNA designs in strong inversion mode, where the design procedures are well established, the design of CMOS weak inversion LNA is still very much in its infancy stage. The design of a CMOS subthreshold LNA presents a considerable challenge because of its simultaneous requirement for high gain, low noise figure, good linearity, good input and output matching and unconditional stability while reducing the power consumption through biasing conditions. The lack of high quality passive components, insufficient study or models of MOS transistors operating in the weak inversion region and the inadequate modeling of the noise sources of the transistor further complicate the design process. The second portion of this research targets on the high bandwidth and linearity requirements of certain wireless applications. Higher bandwidth and data rate enable information intensive signals being transmitted and received, this is extremely true for wireless video streaming or high speed data transfer. To achieve the desired transmission speed is both a system as well as circuit subject. From the system point, modulation scheme adopted as well as frequency planning takes precedence. However it is vital to make use of existing available technology standards and protocols. Wide bandwidth circuits involve frequency switching capability; however, it is difficult to keep a constant power gain ratio across the frequency band. Power gain tolerance issues must be addressed. On top of the wide bandwidth requirement, RF circuit blocks are required to meet the linearity 2 specifications as well. Popular modulation scheme for high data throughput includes frequency division multiplexing (OFDM), quadrature amplitude modulation (QAM) and quadrature amplitude shift keying (QPSK). These schemes require highly linear circuits for operation, which would be discuss further in the later chapters. In light of the shortfalls of the CMOS process, a high performance but slightly more expensive SIGE process has to be adopted instead. A high linearity mixer, buffer and pre-amplifier were designed to meet the transmission specifications of such a wireless application. 1.2 OBJECTIVES The objectives of this project are summarized as follows: (i) (ii) (iii) (iv) (v) To study and understand the various mechanisms which degrade the performance of MOS transistor when biased in the subthreshold region; To study and review suitable amplifiers topologies of CMOS LNA biased in the weak inversion; To study and review performance specific SIGE process; To review suitable transmitter architectures and various topologies for high linearity bipolar junction transistors (BJT) mixers and PAs To design, simulate, layout, fabricate and measure some RF frontend circuits such as LNAs, mixers and PAs. 3 1.3 MAJOR CONTRIBUTIONS OF THE THESIS The major contributions of this thesis are broadly presented in the following subsections: (i) In this project, a simple and novel push pull amplifier design was selected for the design of the LNA. It makes use of current re-use concept to boost the gain of the LNA, as the gain of the MOS transistors biased in the subthreshold region is low. (K.M. Lim et al, A 2.4 GHz Subthreshold CMOS Low Noise Amplifier, Microwave and Optical Letters, Vol. 49, Pg , Feb 2007) (ii) A highly linear mixer, buffer and PA were designed and integrated for a high performance wireless transmitter using SIGE process. Digital controlled varactor tank circuits were used to fulfill the bandwidth requirements. 1.4 ORGANIZATION OF THE THESIS This thesis is organized into 6 chapters. Chapter 1 presents the motivation of this research work. It also defines the objectives of the project and highlights the major contributions of the thesis. Chapter 2 provides a comprehensive literature review of silicon-based transistors as well as silicon passive devices. Various loss mechanisms pertaining to passive devices are discussed as well. 4 Chapter 3 focuses on the high frequency system parameters, the different specifications and derivations of system level performance benchmarks. A brief overall system level design is also introduced. Chapter 4 concentrates on the design and simulation of a low power LNA, with focus on biasing the transistors in the weak inversion region to improve power consumption. Overall performance is tabulated and compared. Chapter 5 verifies the integrated performance of a high bandwidth and highly linear transmitter using the SIGE process. The transmitter making use of non constant envelope modulation scheme is designed, fabricated and packaged, from block level. Testing is performed on a custom flame retardant 4 (FR4) board. Performance is tabulated and compared. Finally, Chapter 6 summarizes the results of this work and recommends a few promising areas for future research. 5 CHAPTER 2 TECHNOLOGY REVIEW Transistors are the basic building blocks of any RF circuit blocks. In this section, we shall focus on two main types of transistors, the bipolar junction transistor (BJT) and the metal oxide semiconductor (MOS) transistor. Both these technologies are very popular process in the industry today, with each technology having its own advantages and disadvantages. For each type of transistor, we briefly introduced their device physics, DC characteristics, high frequency response and their noise contributions. Passive inductors and capacitors, forming tuned loads for RF circuits, are essential building blocks and will be briefly reviewed. 2.1 BIPLOAR JUNCTION TRANSISTORS BJT are composed of two PN junctions placed back to back, forming a three terminal electronic device which regulates current flow [2]. Figure 2-1 shows a cross-sectional view of a typical BJT structure used in integrated circuits. BJT can be further subdivided into NPN transistors and PNP transistors. It comprises of a heavily doped (N + ) emitter region, a lighter doped (N - ) collector region and a superseding (P) base region. Electrical contact to the base region is made through the N + buried layer, the N - layer and the N + contact enhancement region. Isolation from other devices in the circuit is provided by the insulating silicon dioxide layer (SiO 2 ) layer and the p-type substrate. The corresponding symbol representation is shown in Figure Collector Base Emitter P N - P N + P N Buried layer Substrate Figure 2-1: Cross-sectional view of an NPN BJT Under normal operating condition, the emitter-base junction is forward biased while the collector-base junction is reversed biased. In such a configuration, electron carriers for the NPN transistor are injected into the base due to the voltage drive at the emitter junction. The movement of electrons are cause by a combination of both drift and diffusion forces. These electrons move through the base, due to the reverse bias at this junction, the electrons are swept into the collector junction, giving rise to current flow. The current, originating in the emitter is predominately controlled by the voltage across the emitter-base junction and accounts for this structure being an active device. - C - C + V BC + + V BC + B V CE B V CE a) V BE - E b) V BE - E Figure 2-2 : Symbol and sign conventions for (a) NPN transistor; (b) PNP transistor 7 2.1.1 LARGE SIGNAL MODEL A relatively simple, but yet adequate large signal model for the BJT is the Ebers- Moll model [3]. It describes the transistor current in terms of the two PN junctions with their respective voltage across the junctions. In the forward active region, where the base emitter junction is forward biased and the base-collector junction is reversed biased, the relationship can be expressed by equations (2.1), (2.2) and (2.3). I c qadnn = W B po V exp V BE T (2.1) Where V = I s exp V B BE T qadnn I s = W po (2.2) (2.3) Saturation current ( I s ), a constant, is used to describe the transfer characteristic. From analysis, the collector current ( I c ) and the base current ( I B ) are both proportional to the forward current gain ( β ), shown in equation (2.4). F I B I c = β F (2.4) Other operating regions include the saturation and reverse active region, however such regions are usually avoided in analog and RF circuits due to low gain. A graphically representation for equation (2.2) is depicted by Figure 2-3. From the figure, o
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