COMP 300E Operating Systems Fall Semester 2011 Final Examination SAMPLE QUESTIONS

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COMP 300E Operating Systems Fall Semester 2011 Final Examination SAMPLE QUESTIONS Disclaimer: these sample questions should not be used as predictors for the questions in the final exam. These questions
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COMP 300E Operating Systems Fall Semester 2011 Final Examination SAMPLE QUESTIONS Disclaimer: these sample questions should not be used as predictors for the questions in the final exam. These questions are biased towards virtual memory and page replacement, but the final exam will consist of a balanced selection of questions from each chapter. You should also carefully review the sample questions provided on the lecture notes page, as well as the sample and actual midterm exam papers. 1. Single-Choice (Each question has a single correct answer) questions and brief Q&As. * Which of the following is NOT a valid source of cache misses? A. Compulsory B. Capacity C. Conflict D. Trashing ANS: D * Which of the following statement is true for a Fully Associative Cache? A. No conflict misses since a cache block can be placed anywhere. B. More expensive to implement because to search for an entry we have to search the entire cache. C. Generally lower miss rate than a fully-associate cache. D. All of the above ANS: D * Which of the following statement is true for write-through cache and write-back cache? A. A write-through cache will write the value back to memory when it changes. (For example if the value 'x' is stored in the cache and I increment it by one, then the incremented value is written to the cache and to physical memory as well.) B. A write-back cache will only write the value back to memory when the cache block is evicted from the cache. C. All of the above ANS: C * Compare fully-associative cache and direct-mapped cache: cache has lower miss rate; cache has smaller hit time? A. fully-associative, direct-mapped B. direct-mapped, fully associative ANS: A (A fully-associative cache has lower miss rate, since it eliminates conflict misses. A direct-mapped cache has smaller hit time, since cache lookup is a simple table index operation, while a fully-associative cache needs to search through all cache blocks to find a match.) * True or False: TLBs are typically organized as a directly-mapped cache to maximize performance. ANS: False (TLB is usually fully-associative, but can also be set-associative, to minimize miss rate (as compared to fully-associative). Since TLBs are typically very small, the hit time can still be very fast despite the associativity.) * For a single-level page table system, with the page table stored in memory without a TLB. If a memory reference takes 200 nanoseconds, how long does a paged memory reference take? A. 600 nanoseconds B. 200 naboseconds C. 400 nanoseconds D. can't say Ans: C * For a single-level page table system, with the page table stored in memory. If the hit ratio to a TLB is 80%, and it takes 15 nanoseconds to search the TLB, and 150 nanoseconds to access the main memory, then what is the effective memory access time in nanoseconds? A. 185 B. 195 C. 205 D. 175 ANS: B. 0.8*(150+15)+0.2*(300+15)=195 (m + s) h + (2m + s)(1 h) * In a 64 bit machine, with 256 MB RAM, and a 4KB page size, how many entries will there be in the inverted page table? A. 2^16 B. 2^50 C. 2^14 D. None of the above Ans: A Total physical frames is 256MB/4KB=64K=2^16, which is number of PTEs in IPT. * Consider the segment table: What are the physical address for the following logical addresses (Segment ID, Segment Offset) : a. 0,430 b. 1,10 c. 1,11 d. 2,500 ANS: A = 649. B =2310. C =2311 D. Illegal address since size of segment 2 is 100 and the offset in logical address is 500. * In which of the following operations, the OS scheduler is invoked? A. Process requests for I/O. B. Process finishes execution. C. Process finishes its time slot. D. All of the above A through C E. None of the above A through C ANS: D * What happens if the time slice allocated in a Round Robin Scheduling is very large? And what happens if the time slice is very small? ANS: If time slice is very large, it results in FCFS scheduling. If time slice is too small, the processor through put is reduced, since more time is spent on context switching. * What are the two principles of locality that make implementing a caching system worthwhile? ANS: Spatial Locality (If I access a block of data, I am likely to access blocks of data next to it in the future. A simple example is sequentially reading through an array. In this scenario, a caching system with a large block size takes advantage of spatial locality because when I read the first element, I read in seven additional elements so that the next seven reads are from the cache and therefore fast.) Temporal Locality (If I have accessed a block of data before, I am likely to access this block of data again. A simple example is if I have a piece of code that constantly references/updates a global counter.) * True or False: A direct mapped cache can sometimes have a higher hit rate than a fully associative cache with an LRU replacement policy (on the same reference pattern). ANS: True. A direct mapped cache will do better than LRU on a pattern like ABCDEABCDE if the cache size is one entry smaller than the total number of items in the pattern (e.g., four cache entries). LRU will miss on every access, while a direct mapped cache will only miss on the two entries that map to the same cache entry. * True or False: Virtual memory address translation is useful even if the total size of virtual memory (summed over all programs) is guaranteed to be smaller than physical memory. ANS: True. It provides protection between different processes, it doesn t require that each program s addresses be contiguous. * What type of file access pattern exploits spatial locality? ANS: Spatial locality is accessing a location that is close to or next to recently accessed location. Sequential access of a file exploits spatial locality. * Which component of disk access time is the disk scheduling algorithm trying to minimize? ANS: The disk scheduling algorithm is attempting to minimize overall time wasted to moving the disk arm (i.e. it optimizes seek time). * Name at least two ways in which the buffer cache is used to improve performance for file systems. ANS: 1) Reads can be from cache instead of disk 2) Allow delayed writes to disk, thereby permitting better disk scheduling an/or temporary files to be created and destroyed without even being written to disk. 3) Used to cache kernel resources such as disk blocks and name translations * Suppose a new process in a system arrives at an average of six processes per minute and each such process requires an average of 8 seconds of service time. Estimate the fraction of time the CPU is busy in a system with a single processor. ANS: Given that there are on an average 6 processes per minute. So the arrival rate = 6 process/min. i.e. every 10 seconds a new process arrives on an average. Or we can say that every process stays for 10 seconds with the CPU Service time = 8 sec. Hence the fraction of time CPU is busy = service time / staying time = 8 / 10 =0.8 So the CPU is busy for 80% of the time. * If the system does not have enough memory to contain all the processes working sets and is thrashing, and the page replacement algorithm is CLOCK, then does the clock hand move quickly or slowly? Why? ANS: Quickly. Since all pages are hot, so the R bits of all pages are continuously set to 1, the clock hand may come around multiple cycles to find a victim page. And there are a lot of page faults, so the clock hand needs to find victim page to replace very often. * Suppose that we have two-level page tables. Each page is 4KB pages and each Page Table Entry (PTE) is 4 bytes. Suppose we want each page table to occupy exactly one memory page. What is the format of a 32-bit virtual address? ANS: 4 KB = 2^12 bytes, which means page offset is 12 bits to address a specific byte within the page. This leaves us with 20 bits we need to allocate. Since each page is 4 KB and each PTE is 4 bytes, this means that we can fit 4KB/4 bytes=1024 (2^10) PTEs on a page. Since we want each page table to occupy exactly one memory page, each page table should contain 2^10 PTEs. This means that we can use 10 bits to represent each level in the page table. Thus, the breakdown is as follows: 10 bits to reference the correct page table entry in the first level. 10 bits to reference the correct page table entry in the second level. 12 bits to reference the correct byte on the physical page. (Note I will not ask you to draw such a figure in the exam.) * Multi-Level Page Tables (1): Suppose we have a memory system with 32-bit virtual addresses and 4 KB pages. If the page table is full, i.e., there are no null pointers in the page table hierarchy, show that a 20-level page table consumes approximately twice the space of a single level page table. ANS: 4 kilobytes = 2^12 bytes, which means page offset is 12 bits to address a specific byte within the page. This leaves us with 20 bits we need to allocate. We have 20 bits to work with and a 20-level page table, hence there is one-bit in the virtual address for each level of the 20-level page table. Each level of page table consists of 2^1=2 entries (where a '0' bit references the first entry while a '1' bit references the second entry). The total number of page tables in this implementation is therefore: 2^0 + 2^ ^19 = 2^20-1 Since each table has two entries, this means that we have a total of 2^21-2 entries. A single-level page table on the other hand, has 2^20 entries, meaning that there are a total of 2^20 entries in such an implementation. Therefore the 20-level page table consumes approximately twice the space when full. (2) Show that the above is not necessarily true for a sparse page table, where the process memory size is small, and many pointers in the page table hierarchy are null. ANS: Imagine if we only have 1 page of physical memory allocated to a process. This means that we have only 20 tables, since we just need one entry per level of indirection. Each table has 2 entries, so we have a total of 40 entries for our page table implementation. In the single-level case, in the sparse memory scenario, we still have 2^20 entries allocated, meaning that the 20-level page table is theoretically feasible for sparse memory usage (although 20 memory accesses to determine a translation is still expensive and therefore not practical). * Page replacement For the following problem, assume a hypothetical machine with 4 pages of physical memory and 7 pages of virtual memory. Given the access pattern: A B C D E F C A A F F G A B G D F F Indicate in the following table which pages are mapped to which physical pages for each of the following policies. If there is no page fault at that time-step, leave the column blank. Here MIN refers to OPT (optimal policy) * For the following problem, assume a hypothetical machine with 4 pages of physical memory and 7 pages of virtual memory. Given the access pattern: A B C D E A A E C F F G A C G D C F Indicate in the following table which pages are mapped to which physical pages for each of the following policies. Assume that a blank box matches the element to the left. We have given the FIFO policy as an example. * Consider a virtual memory architecture with the following parameters: Virtual addresses are 48 bits. Hence the architecture has virtual address space of 64 Terabytes (TB), i.e., it allows a maximum of 64TB physical memory (RAM). (1TB=10^12 =2^40bytes) The page size is 32KB. The first- and second-level page tables are stored in physical memory. All page tables can start only on a page boundary. Each second-level page table fits exactly in a single page frame. Each Page Table Entry (PTE) is 32 bits, consisting of 31-bit PPN and 1 valid bit, for both 1 st and 2 nd -level page tables. Assume there is a single valid bit for each PTE and no other extra permission, or dirty bits. Draw and label a figure showing how a virtual address gets mapped into a real address. You should list how the various fields of each address are interpreted, including the size in bits of each field, the maximum possible number of entries each table holds, and the maximum possible size in bytes for each table (in bytes). ANS: The page size is 32KB Page offset is 15 bits. A 32 KB page can thus hold 8K 4-byte PTEs, and each second-level page table fits exactly in a single page frame, hence each 2 nd level page table has 8K entries. So we should allocate 13 bits (2^13=8K) to the 2 nd level page table, and 20 bits ( ) to the 1 st level page table. The first-level page table has 2^20 (1 million) entries, each of which is 32 bits (31-bit PPN plus valid bit, or 4 bytes), so it has a maximum size of 4 MB. (Note I will not ask you to draw such a figure in the exam.)
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