AND9383/D. AX50324 Programming Manual APPLICATION NOTE

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AX50324 Programming Manual DEVICE OVERVIEW The AX50324 is a fully integrated transmitter chip for a Satellite Messaging System. Figure 1 shows a simplified block diagram of the AX APPLICATION NOTE
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AX50324 Programming Manual DEVICE OVERVIEW The AX50324 is a fully integrated transmitter chip for a Satellite Messaging System. Figure 1 shows a simplified block diagram of the AX APPLICATION NOTE Figure 1. AX50324 Block Diagram Semiconductor Components Industries, LLC, 2016 September, 2016 Rev. 3 1 Publication Order Number: AND9383/D TABLE OF CONTENTS Device Overview... 1 Features... 3 AX Registers Address Space Flash Cache and prefetch RAM Debug Interface System controller DMA Controller GPIO ADC, Comparator, Temperature Sensor SPI Master/Slave Interface Timer counter 0/1/ Output Compare 0/ Input Capture UART 0/ Satellite Transmitter FEATURES Satellite Transmitter High Power High Efficiency Transmitter PA Voltage Regulator Ensures Consistent Output Power in the Presence of Supply Voltage Changes Digital Modulator Provides Accurate, no Trimming Needed, Waveforms and Suppresses Out-of-Band Emissions Integrated PLL for Carrier Generation Requiring no External Components Fully Autonomous Message Generator Performs all Transmit Sequencing without CPU Intervention Independent Power Modes Allows the CPU to Sleep while the Transmitter Sends a Message 8052 Industry Standard 8052 Instruction Set High Performance Core, Most Instructions Require only 1 Clock per Instruction Byte 20 MIPS Dual DPTR for High Speed External Memory Copies 22 Interrupt Vectors Debugger 3 Wire (1 Dedicated, 2 Shared with GPIO Pins) Debugger Interface True Hardware Debugger with Breakpoints and Single Stepping Support User Programmable 64 bit Key to Restrict Debugging to Authorized Personnel DebugLink Interface Allows printf Style Debugging without Utilizing a UART or GPIO Pins Memory 64 kbyte FLASH 8.25 kbyte RAM High Performance Memory Crossbar Clocking Flexible Clocking Options Thanks to an On-Chip 20 MHz Fast RC Oscillator, 10 khz/640 Hz Low Power RC Oscillator, Fast Crystal Oscillator, Low Power Tuning Fork Crystal Oscillator, Dedicated TCXO Input Fully Automatic Calibration of On-Chip RC Oscillators to a Reference Clock Clock Monitor can Detect Failures of the Main Clock and Switch to the On-Chip Fast RC Oscillator Watchdog Power Modes Standby, Sleep and Deep Sleep Power Modes for Very Low Idle Power Consumption On-Chip Power-On Reset and Brown Out Detection Unrestricted Operation from V VDDD and V VDD_RF 16 Bit Wakeup Timer 2 Counting registers 4 Event registers allow flexible wakeup and software schedules GPIO 20 GPIO pins PB0 PB7 and PC0-PC 5 5 V tolerant inputs All GPIO Pins Support Individually Programmable Pull-Ups and Interrupt On Change Flexible Allocation of GPIO Pins to Peripherals 3 16 Bit General Purpose Timer Sawtooth and Triangle Modes Sigma-Delta Mode Converts Timer Into a DAC Optional Double Buffering of the PERIOD Register Allows Controlled Frequency Changes Optional High-Byte Buffering Allows Atomic 16 bit Accesses Flexible Clocking Options, Can Use Any Internal or an External Clock Source, Prescaler Included 2 16 Bit Output Compare Units Used Together with a General Purpose Timer to Create PWM Waveforms Optional Double Buffering 2 16 Bit Input Capture Units Used Together with a General Purpose Timer to Time Events on an External or Internal Signal 2 UARTs 5 9 bit Word Length, 1 2 Stop Uses One of the General Purpose Timers as Baud Rate Generator Master/Slave SPI ADC 10 Bit 500 ksamples/s ADC Up to 8 Channels Single Ended and Differential Sampling x0.1, x1 and x10 Gain Amplifier (Single Ended x1 and x10) Internal 1 V or External Reference Flexibly Programmable Conversion Schedule Built-In Temperature Sensor Analog Comparators Internal or External Reference Output Signal May be Routed to GPIO, Read by Software, or Used as Input Capture Trigger DMA Controller 2 Independent DMA Channels Moves Data Between X-RAM and Most On-Chip Peripherals Cycle-Steal and Round-Robin Memory Arbitration Ensure Minimal Impact on 8052 Core Chained Buffer Descriptors Allow Arbitrarily Elaborate Buffering Schemes and Flexible Interrupt Generation 3 AX8052 The AX8052 core is fully compatible with the MCS 51 instruction set. Standard 803x/805x assembler and compilers can be used to develop software. The peripherals however are vastly improved and therefore not compatible with other 8051/8052 implementations. Performance The AX8052 core employs a pipelined architecture that greatly increases its instruction throughput over the standard 8052 architecture. Instead of using 12, 24 or 48 clock cycles to execute instructions, AX8052 requires between 1 and 11 clock cycles depending on instructions. 90% of the instructions are executed between 1 and 4 clock cycles. Table 1. AX8052 PERFORMANCE Clocks to execute instructions There is one clock cycle latency when reading data in the IRAM. It does not concern internal SFR read and write accesses nor IRAM write accesses. Those instructions are indicated with an plus (+) in the instruction set summary table, indicating that the latency depends on the memory space access. Instructions doing read or write accesses to the external SFR memory space are also indicated with an plus (+) as the latency depends on the peripheral. There is as well one clock cycle latency when reading data in the XRAM. It is not the case for write accesses. The 4 register banks are located in the IRAM. So R0 and R1 of the active register bank selected by PSW[4:3] are not easily accessible when doing indirect addressing. In order to speed up this addressing mode, the core has two internal shadow registers to store R0 and R1 images. Doing so, it is not necessary to read R0 or R1 each time the core makes an indirect access. Nevertheless, instructions that change PSW[4:3] flags require 4 clock cycles more in order to read the new active R0 and R1. The bit addressable locations are also in the IRAM. Writing a bit to such memory locations implies a Read-Modify-Write operation, and so requires 2 clock cycles to read the byte and modify the appropriate bit, and one clock cycle to write the new byte in the IRAM. Instruction Set All the AX8052 instructions are the binary and functional equivalent of the 8051 counterparts, including opcodes, addressing modes and effects on PSW. The next table named Instruction set summary provides information about the arithmetic, logical, data transfer, boolean manipulation and program branching instructions. In order to simplify the table, different symbols are used. Their meanings are: Rn: Register R0 R7 of the currently selected register Data RAM location addressed indirectly through R0 or R1. Rel: 8-bit, signed (2 s complement) offset relative to the first bytes of the following instruction. Direct: 8-bit internal data location s address. This could be direct access Data RAM location (0x00 0x7F) or an SFR (0x80 0xFF). #data: 8 or 16-bit constants. Bit: Direct-accessed bit in Data Ram or SFR. Addr11: 11-bit destination address used by ACALL and AJMP. The destination must be within the same 2K-bytes page of program memory as the first byte of the following instruction. Addr16: 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within the program memory. Table 2. INSTRUCTION SET SUMMARY Instruction Description Prgm Bytes Clock Cycles ARITHMETIC OPERATIONS ADD A, Rn Add register to Accumulator 1 2 ADD A, direct Add direct byte to Accumulator 2 2+ ADD Add indirect RAM to Accumulator 1 2 ADD A, #data Add immediate data to Accumulator 2 2 ADDC A, Rn Add register to Accumulator with carry 1 2 ADDC A, direct Add direct byte to Accumulator with carry 2 2+ ADDC Add indirect RAM to Accumulator with carry 1 2 ADDC A, #data Add immediate data to ACC with carry 2 2 SUBB A, Rn Subtract Register from ACC with borrow 1 2 SUBB A, direct Subtract direct byte from ACC with borrow Table 2. INSTRUCTION SET SUMMARY (continued) Instruction Description Prgm Bytes Clock Cycles ARITHMETIC OPERATIONS SUBB Subtract indirect RAM from ACC with borrow 1 2 SUBB A, #data Subtract immediate data from ACC with borrow 2 2 INC A Increment Accumulator 1 1 INC Rn Increment register 1 3 INC direct Increment direct byte 2 3+ Increment indirect RAM 1 3 INC DPTR Increment Data Pointer 1 1 DEC A Decrement Accumulator 1 1 DEC Rn Decrement Register 1 3 DEC direct Decrement direct byte 2 3+ Decrement indirect RAM 1 3 MUL AB Multiply A and B 1 11 DIV AB Divide A by B 1 11 DA A Decimal Adjust Accumulator 1 1 LOGICAL OPERATIONS ANL A, Rn AND Register to Accumulator 1 2 ANL A, direct AND direct byte to Accumulator 2 2+ ANL AND indirect RAM to Accumulator 1 2 ANL A, #data AND immediate data to Accumulator 2 2 ANL direct, A AND Accumulator to direct byte 2 3+ ANL direct, #data AND immediate data to direct byte 3 3+ ORL A, Rn OR register to Accumulator 1 2 ORL A, direct OR direct byte to Accumulator 2 2+ ORL OR indirect RAM to Accumulator 1 2 ORL A, #data OR immediate data to Accumulator 2 2 ORL direct, A OR Accumulator to direct byte 2 3+ ORL direct, #data OR immediate data to direct byte 3 3+ XRL A, Rn Exclusive OR register to Accumulator 1 2 XRL A, direct Exclusive OR direct byte to Accumulator 2 2+ XRL Exclusive OR indirect RAM to Accumulator 1 2 XRL A, #data Exclusive OR immediate data to Accumulator 2 2 XRL direct, A Exclusive OR Accumulator to direct byte 2 3+ XRL direct, #data Exclusive OR immediate data to direct byte 3 3+ CLR A Clear Accumulator 1 1 CPL A Complement Accumulator 1 1 RL A Rotate Accumulator left 1 1 RLC A Rotate Accumulator left through the carry 1 1 RR A Rotate Accumulator right 1 1 RRC A Rotate Accumulator right through the carry 1 1 SWAP A Swap nibbles within the Accumulator 1 1 5 Table 2. INSTRUCTION SET SUMMARY (continued) Instruction Description Prgm Bytes DATA TRANSFER MOV A, Rn Move register to Accumulator 1 1 MOV A, direct Move direct byte to Accumulator 2 2+ MOV Move indirect RAM to Accumulator 1 1 MOV A, #data Move immediate data to Accumulator 2 2 MOV Rn, A Move Accumulator to register 1 1 MOV Rn, direct Move direct byte to register 2 3+ MOV Rn, #data Move immediate data to register 2 2 MOV direct, A Move Accumulator to direct byte 2 2+ MOV direct, Rn Move register to direct byte 2 3+ MOV direct, direct Move direct byte to direct 3 3+ MOV Move indirect RAM to direct byte 2 3+ MOV direct, #data Move immediate data to direct byte 3 3+ A Move Accumulator to indirect RAM 1 1 direct Move direct byte to indirect RAM 2 3+ #data Move immediate data to indirect RAM 2 2 MOV DPTR, #data Load Data Pointer with a 16-bit constant 3 3 MOVC Move Code byte relative to DPTR to ACC 1 4 MOVC Move Code byte relative to PC to ACC 1 4 A Move Accumulator To Program Memory 1 4 MOVX Move external RAM (8-bit addr) to ACC 1 2 MOVX Move external RAM (16-bit addr) to ACC 1 2 A Move ACC to external RAM (8-bit addr) 1 1 A Move ACC to external RAM (16-bit addr) 1 1 PUSH direct Push direct byte onto stack 2 3+ POP direct Pop direct byte from stack 2 3+ XCH A, Rn Exchange register with Accumulator 1 3 XCH A, direct Exchange direct byte with Accumulator 2 3+ XCH Exchange indirect RAM with Accumulator 1 3 XCHD Exchange low-order digit indirect RAM with ACC 1 3 BOOLEAN MANIPULATION CLR C Clear carry 1 1 CLR bit Clear direct bit 2 4 SETB C Set carry 1 1 SETB bit Set direct bit 2 4 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 6 ANL C, bit AND direct bit to carry 2 3 ANL C, /bit AND complement of direct bit to carry 2 3 ORL C, bit OR direct bit to carry 2 3 ORL C, /bit OR complement of direct bit to carry 2 3 MOV C, bit Move direct bit to carry 2 3 Clock Cycles 6 Table 2. INSTRUCTION SET SUMMARY (continued) Instruction Description Prgm Bytes BOOLEAN MANIPULATION MOV bit, C Move carry to direct bit 2 4 JC rel Jump if carry is set 2 3 JNC rel Jump if carry not set 2 3 JB rel Jump if direct bit is set 3 5 JNB rel Jump if direct bit is not set 3 5 JBC bit, rel Jump if direct bit is set and clear bit 3 7 PROGRAM BRANCHING ACALL addr11 Absolute subroutine call 2 3 LCALL addr16 Long subroutine call 3 4 RET Return from subroutine 1 6 RETI Return from interrupt 1 6 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump (relative addr) 2 3 Jump indirect relative to the DPTR 1 3 JZ rel Jump if Accumulator is zero 2 3 JNZ rel Jump if Accumulator is not zero 2 3 CJNE A, direct, rel Compare direct byte to ACC and jump if not equal 3 4+ CJNE A, #data, rel Compare immediate to ACC and jump if not equal 3 4 CJNE Rn, #data, rel Compare immediate to register and jump if not equal 3 5 #data, rel Compare immediate to indirect and jump if not equal 3 5 DJNZ Rn, rel Decrement register and jump if not zero 2 4 DJNZ direct, rel Decrement direct byte and jump if not zero 3 4+ NOP No Operation 1 1 Clock Cycles 7 Memory Organization Figure 2. AX8052 Memory Organization Data Memory The AX8052 has 256 bytes of data memory mapping called IRAM (Internal Data) or SFR (Special Function Register) depending on the addressing mode used and the address space access. The memory space goes from 0x00 to 0xFF. The lower 128 bytes of data memory are used for general purpose registers, bits and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory: Location 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. 8 The next 16 bytes locations 0x20 through 0x2F may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. The upper 128 bytes region represents the upper part of internal data memory and the SFR. They are physically separated and are accessible through different addressing modes: The upper 128 bytes of internal data memory is accessible only with indirect addressing. Special Function Registers are accessible on the same address space, using direct addressing. Register Banks The AX8052 uses 8 R registers (locations 0x00 through 0x1F) which are used in many instructions. These R registers are numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, R7) and are generally used to assist in manipulating values and moving data from one memory location to another. The microcontroller has 4 distinct register banks and only one of these banks may be enabled at a time. When the CPU is first booted up, register bank 0 is used by default. However, your program may instruct the CPU to use one of the alternate register banks; i.e., register bank 1, 2 or 3. In this case, R4 (for example) will no longer be the same as internal RAM address 04h. Two bits in the Program Status Word (PSW), RS0 (PSW.3) and RS1 (PSW.4), select the active register bank. Indirect addressing mode uses registers R0 and R1 as index registers. The AX8052 has a directly accessible image of the active R0 and R1, speeding up indirect accesses. Doing so, the core does not need to read R0 or R1 in IRAM before doing an indirect access. Each time the active R0 or R1 register is changed, or when RS0 and/or RS1 is modified, the core updates the R0 and R1 images. Register bank 3 0x18 R0 R1 R2 R3 R4 R5 R6 R7 RS0=1 RS1=1 Register bank 2 0x10 R0 R1 R2 R3 R4 R5 R6 R7 RS0=0 RS1=1 Register bank 1 0x08 R0 R1 R2 R3 R4 R5 R6 R7 RS0=1 RS1=0 Register bank 0 0x00 R0 R1 R2 R3 R4 R5 R6 R7 RS0=0 RS1=0 IRAM 0x00 0x1F Figure 3. Register Banks Bit Addressable Locations The sixteen data memory location at 0x20 through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from 0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by the type of instruction used (bit source or destination operands as opposed to a byte source or destination). 0x2F 0x IRAM 0x20 0x2F Figure 4. Bit Memory Stack A programmer s stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is place at SP+1, and then SP is incremented. A reset initializes the stack pointer to location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. Special Function Registers (SFR) The direct access data memory locations from 0x80 to 0xFF constitute the Special Function Registers (SFRs). The internal SFR are the accumulator (A or ACC), the B register (B), the Stack Pointer (SP), the Program Status Word (PSW), the Interrupt Enable (IE) and Interrupt priority (IP) registers and the external Data Pointer register (DPL and DPH, known as DPTR). The word internal is used to describe those SFR because they are physically located inside the AX8052 core. In opposition to internal SFR, it exists external SFRs that provide control and data exchange with the AX8052 and peripherals (like ports, timers, UARTS...). The word external is used because the peripherals implementing those SFR are located outside the core. Direct addressing mode is used to access the SFR memory location, i.e. from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. ACC, B, PSW, IP, IE ) are bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are reserved for future use (peripherals...). Accessing these areas will have an indeterminate effect and should be avoided. 9 Internal SFR descriptions ACCUMULATOR A Table 3. ACCUMULATOR A R/W R/W R/W R/W R/W R/W R/W R/W ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 Reset Value: 0x00 SFR Address: 0xE0 Bit Addressable: Yes 7 0: Accumulator (A) B REGISTER B Table 4. B REGISTER B R/W R/W R/W R/W R/W R/W R/W R/W B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 Reset Value: 0x00 SFR Address: 0xF0 Bit Addressable: Yes 7 0: B register (B). This register serves as a second accumulator for some arithmetic operations. STACK POINTER SP Table 5. STACK POINTER SP R/W R/W R/W R/W R/W R/W R/W R/W SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 Reset Value: 0x07 SFR Address: 0x81 Bit Addressable: No 7 0: Stack Pointer (SP). The stack pointer holds the top location of the stack. It is incremented before every PUSH operations and decremented after every POP operations. PROGRAM STATUS WORD PSW Table 6. PROGRAM STATUS WORD PSW R/W R/W R/W R/W R/W R/W R/W R CY AC F0 RS1 RS0 OV F1 P Reset Value: 0x00 SFR Address: 0xD0 Bit Addressable: Yes Bit 7: Carry Flag (CY). This bit is set when the last arithmetic operation resulted in carry into (addition) or a borrow (subtraction). It is cleared to 0 by all other arithmetic operations. Bit 6: Auxiliary Carry Flag (AC). This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow (subtraction) from the higher order nibble. It is cleared to 0 by all other arithmetic operations. Bit 5: User Flag 0 (F0). This is a bit-addressable, general purpose flag for use under software control. Bit 4 3: Register Bank Select (RS1 RS0). These bits select which register bank is used during register access. 0 0: Register Bank 0 is selected 0 1: Register Bank 1 is selected 1 0: Register Bank 2 is selected 1 1: Register Bank 3 is selected Bit 2: Overflow Flag (OV). This bit is set to 1 under the following circumstances: An ADD, ADDC or SUBB instruction causes a sign-change overflow. A MUL instruction results in an overflow (result is greater than 255). A DIV instruction causes a divide-by-zero condition. Bit 1: User Flag 1 (F1). This is a bit addressable, general purpose flag for use under software control. Bit 0: Parity Flag (P). This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. DATA POINTER DPTR Table 7. DATA POINTER DPTR R/W R/W R/W R/W R/W R/W R/W R/W DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0 Reset Value:
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