2: The MCF51JM Microcontroller

Please download to get full document.

View again

of 63
All materials on our website are shared by users. If you have any questions about copyright issues, please report us to resolve them. We are always happy to assist you.
Information Report
Category:

Recipes/Menus

Published:

Views: 2 | Pages: 63

Extension: PPTX | Download: 0

Share
Related documents
Description
Download 2: The MCF51JM Microcontroller
Transcript
Slide1

2:The MCF51JM Microcontroller

CET360

Microprocessor Engineering

J

. Sumey

ver. 2/03/15

Slide2

2

MCF51JM Overview

32-bit ColdFire (V1) MCU w/ USB

2.7~5.5V, up to 50 MHz

descendent of the 68000 (68k) family

same register set

based on high-performance RISC CPU

32-bit data bus, PC, registers, ALU!

24-bit address bus

2-stage pipelines for each instructions and operands

2 operational modes: user, supervisor

extensive

library of on-board peripheral modules

multiple operational modes

single-wire

background debug capability (BDM)

Slide3

3

MCF51JM Modules

Memory: Flash (128KB), RAM (16KB)

ACMP

: analog comparator

ADC

: 12-bit analog-to-digital (12 channels)

BDM

: background debug support, single-wire

CAN

: controller area network

CMT

: carrier modulator timer

COP

: computer operating properly

IIC

: inter-integrated circuit serial bus

KBI

: keyboard interrupt (8 inputs)

LVD

: low voltage detector

MCG

: multipurpose clock generator

GPIO

: I/O ports (51 GP + 6 Rapid GP pins)

RTC

: real-time counter

SCI

,

SPI

: serial interfaces (2 SCI, 2 SPI)

TPM

: timer/pulse-width modulator (6+2 channels)

USBOTG

: host/device support (dual-role)

Slide4

4

Slide5

5

MCF51JM Packages

available in QFP, LQFP packages44, 64, 80 pinsFirebird32 uses 64-pin version on a 40-pin DIP module

Slide6

6

Memory Map

MCU is von NeumannRAM, ROM, IO Registers exist in single map24-bit address bus -> 16 MB address space128K FLASH: 0x00_0000..0x01_FFFFincludes vectors16K RAM: 0x80_0000..0x80_3FFFIO Registers: 0xFF_8000..0xFF_FFFFsee Reference Manual

Slide7

performs all computation / instruction execution(CFPRM ColdFire Programmer’s Ref. Manual)

ColdFire CPU

Slide8

Programming Model – User Mode

16 general-purpose 32-bit registers (8 Data + 8 Address)32-bit program counter, PC (top 8 bits forced to zero)8-bit condition code register, CCRA7 doubles as SPthis is User mode, Supervisor mode has additional registers…

8

Condition Code Register

X: sign extend

N: Negative flag

Z: Zero flag

V: signed overflow

C: unsigned overflow

Slide9

Programming Model - Supervisor

adds additional CPU registers for "privileged" operationsMCF51JM includes:16-bit status register, SR (CCR is lower byte)supervisor SP, OTHER_A7VBR sets base address of vector table (defaults to 0)

9

Slide10

Status Register (SR) Details

system byte only available in supervisor modeT: 1=trace enableS: 0=user mode, 1=supervisor modeM: 1=master state, 0=interrupt stateI: sets interrupt mask level 0..70 = all interrupts enabled1 = all interrupts disabled (except IRQ pin)

10

Slide11

Instruction Format

‘word’ = 16 bits (32 bits = ‘longword’)first word is instruction “op word”specifies operation, instruction length, EA modeadditional words specify operands

11

Slide12

12

ColdFire Addressing Modes

Addr

. Mode

Generation

Description

Immediate

Operand given

Operand is byte, word, or

longword

after

opword

(use ‘#’ in assembly)

Absolute Short

EA given

16-bit operand EA follows instruction

opword

Absolute Long

EA given

32-bit operand EA follows instruction

opword

Data Register Direct

EA=

Dn

Operand is in a Data register

Address Register Direct

EA=An

Operand is in an Address register

Address Register Indirect

EA=(An)

Address register contains EA of operand

Address Register Indirect with

Postincrement

EA=(An); An += Size

Address register contains EA of operand & gets incremented after use

Address Register Indirect with

Predecrement

An -= Size; EA=(An)

Address register is first decremented then contains EA of operand

Address Register Indirect with Displacement

EA = (An)+d

16

Operand address is sum of address register plus 16-bit signed displacement

Program Counter Indirect with Displacement

EA = (PC)+d

16

Operand address is sum PC plus 16-bit signed displacement

Slide13

ColdFire Instruction Set Summary

organized by type of operationdata movementprogram controlinteger arithmeticfloating-point arithmetic (when FPU available)logical operationsshift operationsbit manipulationsystem controlcache maintenance

13

Slide14

provides interface to general purpose I/O pins(MCF51JM ColdFire Ref. Manual, ch. 9)

Parallel I/O Ports

Slide15

I/O Ports

up to 70 i/o pins on up to 9 portsnamed A..Ieach port has i/o register and DDRalso have pull-up, slew rate, drive strength, and interrupt control registersnaming convention: PTxD, PTxDDex: PTAD, PTEDDref: table 4-2 in ref. manualindividual bit accessex: PTBD_PTBD2 = 1;

15

Slide16

provides hardware time counting functions with optional interrupt(MCF51JM ColdFire Ref. Manual, ch. 17)

Real-Time Counter (RTC) Module

Slide17

RTC Components

strictly internal, no external pinsthree input clock sources, software selectable1 kHz internal low-power oscillator (LPO)32 kHz internal clock (IRCLK)external clock (ERCLK)software-programmable prescaler8-bit up counter with 8-bit modulo match comparatorsoftware controlled interrupt on modulo match

17

Slide18

RTC Block Diagram

18

shaded boxes represent RTC registers

Slide19

RTC Register Summary

only three 8-bit registers:RTCSC = RTC Status and Control registerRTCCNT = 8-bit RTC Counter registerRTCMOD = 8-bit Modulo register

19

Slide20

RTC Status / Control Register

RTIF (b7): Real-Time Interrupt Flagsets when counter reaches modulo registerclear by writing a 1RTCLKS (b6-5): Real-Time Clock Source Selectchooses RTC clock input source00=LPO, 01=ERCLK, 1x=IRCLKRTIE (b4): Real-Time Interrupt Enableenables RTC interrupts to CPU (when 1)RTCPS (b3-0): Real-Time Clock Prescaler Selectchooses binary- or decimal-based divide-by valuessee table in ref. manual

20

Slide21

RTC Usage Example

msdelay(): a very precise ms delay functionrequires RTCMOD > 0this version does not use RTIF leaving the RTC modulo feature fully available

21

//

msdelay

(): delay given number of milliseconds using Real-Time Counter module

void

msdelay

(

int

n)

{

while

(n-- > 0) {

byte

ctr

= RTCCNT;

// take copy of current RTC Counter register

while (RTCCNT ==

ctr

) {}

// wait till it changes

}

}

// include in initialization code:

RTCSC

= 0x08;

// enable RTC, select 1ms period from 1kHz internal clock

Slide22

prioritizes all system exceptions and performs all vector handling(MCF51JM Coldfire Ref. Manual, ch. 8 and ColdFire Programmer’s Ref. Manual, ch. 11)

INTerrupt

Controller

(INTC) Module

Slide23

23

Exception Handling

Exception

: an unscheduled (but

sometimes planned

) event that causes the CPU to depart

(i.e. abort) from

the normal fetch-decode-execute cycle

may

or may not be

fault

related

Exception processing:

copy the Status Register (SR) then set SR[S] to switch to

supervisor mode

determine the appropriate exception

vector number

based on source/cause of exception

save current context (PC, SR) in an 8-byte

exception frame

on the

system stack

(A7’)

fetch to PC address of

exception handler

from

vector table

; resume normal instruction processing

exception handler must end with RTE instruction, after which the interrupted instruction is restarted

Slide24

Vector Table

ColdFire vector tableup to 256 vectors, 4-bytes eacheach vector contains address of respective exception handlerfirst 64 for CPU, 192 for other usesi.e. peripheral/software/etc.Vector Base Register (VBR) points to begin of tablethis is a supervisor mode registerby default, table begins at location 0uses 1st 1 KiB of memory mapMCF51JM exceptions:defines 64 for CPU + 39 for peripheral IRQs (103 total)

24

Slide25

VectorNumberVectorOffsetAssignment0000Initial stack pointer1004Initial program counter2008Access error300CAddress error4010Illegal instruction5014Divide by zero6-7018-01CReserved8020Privilege violation9024Trace10028Unimplemented line-A opcode1102CUnimplemented line-F opcode12030Non-PC breakpoint debug interrupt13034PC breakpoint debug interrupt14038Format error1503CUninitialized interrupt

ColdFire Exception Vectors (1/2)

25

Slide26

VectorNumberVectorOffsetAssignment16-23040-05CReserved24060Spurious interrupt25-31064-07CLevel 1-7 autovectored interrupts32-47080-0BCTrap #0-15 instructions480C0Floating-point branch on unordered condition490C4Floating-point inexact result500C8Floating-point divide-by-zero510CCFloating-point underflow520D0Floating-point operand error530D4Floating-point overflow540D8Floating-point input not-a-number (NAN)550DCFloating-point input denormalized number56-600E0-0F0Reserved610F4Unsupported instruction62-630F8-0FCReserved64-255100-3FCUser-defined interrupts (I/O peripherals)

ColdFire Exception Vectors (2/2)

26

Slide27

VectorNumberVectorOffsetAssignment64100IRQ (pin)65104Low Voltage Detect66108Loss of Lock6710CSPI168110SPI269114USB_Status70118-7111CTPM1 Channel 072120TPM1 Channel 173124TPM1 Channel 274128TPM1 Channel 37512CTPM1 Channel 476130TPM1 Channel 577134TPM1 Overflow78138TPM2 Channel 07913CTPM2 Channel 180140TPM2 Overflow

MCF51JM Exceptions (1/2)

27

Slide28

VectorNumberVectorOffsetAssignment81144SCI1 Error82148SCI1 Receive8314CSCI1 Transmit84150SCI2 Error85154SCI2 Receive86158SCI2 Transmit8715CKBI Interrupt88160ADC Conversion89164ACMP90168IIC19116CRTC92170IIC293174CMT94178CAN Wakeup9517CCAN Error96180CAN Receive97184CAN Transmit98188RNGA Error104-1101A0-1BCForce_lvli (i=7..1)

MCF51JM Exceptions (2/2)

28

Slide29

Interrupt Dispositions

some interrupts are non-maskable but most are maskableprogrammer can enable / disable at willCPU CCR contains a 3-bit interrupt priority field for controlling maskable interrupts0..7, any level below current setting is disabledresets to 7CodeWarrior’s hidef.h file contains relevant macrosEnableInterrupts: sets level to 0DisableInterrupts: sets level to 7derivative.h defines all vector numbersex:

29

#define

VectorNumber_Vrtc

91U

Slide30

Spoiler alert! (how to program an ISR)

ex: an ISR to handle RTC interruptsmust also enable interrupts in the RTCSC register, i.e. RTIE must be set!ISRs can neither accept or return arguments"interrupt" causes '}' to be an RTE instead of RTS

30

//

rtc_isr

(): process interrupts from RTC module

interrupt

VectorNumber_Vrtc

void

rtc_isr

(void)

{

RTCSC_RTIF = 1;

// acknowledge & reset RTIF

flag

// process RTC event – timekeeping, update LEDs, etc.

⋮

}

Slide31

a peripheral module providing 28 channels of 8-, 10- or 12-bit A/D conversion(MCF51JM ColdFire Ref. Manual, ch. 21)

ADC Module

Slide32

32

ADC Features

28 input

channels

(12 externally available)

8-, 10- or 12-bit resolution

right justified, unsigned result

selectable ADC clock

conversion time under 2 us possible!

per command or continuous conversion modes

internal temperature sensor

one interrupt source

conversion complete

Slide33

33

ADC Module Components

conversion clock selection & prescaler

32 inputs via analog multiplexer

successive approx. register (SAR)

compare function

interrupt logic

Slide34

34

ADC Block Diagram

Slide35

ADC Register Map

35

Address Offset Register NameFunctionDescription0x0000ADCSC1Status and Control Register 1selects channel, conversion mode, interrupt enable; provides conversion complete status (COCO)0x0001ADCSC2Status and Control Register 2sets conversion trigger and compare features0x0002ADCRHData Result High Registertop 2 (10-bit) or 4 (12-bit) bits of ADC result0x0003ADCRLData Result Low Registerbottom 8 bits of ADC result0x0004ADCCVHCompare Value High Registerhigh byte of compare value (when enabled)0x0005ADCCVLCompare Value Low Registerlow byte of compare value (when enabled)0x0006ADCCFGConfiguration Registerselects ADC clocking, sample time, # bits (8,10,12)0x0007APCTL1Pin Control 1 Registerdisables pin I/O control, channels 0-70x0008APCTL2Pin Control 1 Registerdisables pin I/O control, channels 8-15

Above addresses are offsets from ADC base address (0xFFFF8010).

Slide36

ADC Channel Assignments (MCF51)

36

ADCH*ChannelInput00000AD0PTB0/MISO2/ADP000001AD1PTB1/MOSI2/ADP100010AD2PTB2/SPSCK2/ADP200011AD3PTB3/SS2/ADP300100AD4PTB4/KBIP4/ADP400101AD5PTB5/KBIP5/ADP500110AD6PTB6/ADP600111AD7PTB7/ADP701000AD8PTD0/ADP8/ACMP+01001AD9PTD1/ADP9/ACMP-01010AD10PTD3/KBIP3/ADP1001011AD11PTD4/ADP1101100AD12VREFL01101AD13VREFL01110AD14VREFL01111AD15VREFL

ADCH*ChannelInput10000AD16VREFL10001AD17VREFL10010AD18VREFL10011AD19VREFL10100AD20VREFL10101AD21VREFL10110AD22Reserved10111AD23Reserved11000AD24Reserved11001AD25Reserved11010AD26Temperature Sensor11011AD27Internap bandgap11100-Reserved11101VREFHVDD11110VREFLVSS11111ADC offNone

*bottom 5 bits written to the ADCSC1 register

Slide37

37

ADC Application (no compare)

initialization or per conversion

:

select ADC clock source & divide-by, # bits for conversion (

ADCCFG

)

set pin control register bit(s) to switch between port i/o or ADC function

ADPCx

: 0=port

i

/o, 1=A/D function

per conversion

:

select channel to convert (

ADCSC1

)

wait for conversion complete (

COCO

)

read data from result registers (

ADCRx

)

Slide38

38

ADC Example

#include “mcf51jm128.h”// ADC initialization:ADCCFG = (0b10 << ADCCFG_ADIV_BITNUM) // select Busclk/4 (3MHz) + (0b10 << ADCCFG_MODE_BITNUM); // 10-bit modeADPC1_ADPC4 = 1; // select A/D for channel 4 pin// perform conversionADCSC1 = 4; // start conversion on PTB4while (!ADCSC1_COCO){} // wait for conversion complete*int adcresult = ADCR; // grab 2-byte result

*can also use “WAITFOR” macro here! i.e.:

WAITFOR(ADCSC1_COCO);

Slide39

a highly flexible peripheral module used to perform timing-relatedtasks in hardware(MCF51JM ColdFire Ref. Manual, ch. 22)

Timer/PWM (TPM) Module

Slide40

40

TPM Features

two TPMs

TPM1 has 6 channels, TPM2 has 2

optionally uses PortE,F bits for external I/O

input capture

measure characteristics of input pulses/signals

output compare

generation of programmer-defined signals

pulse/periodic, frequency, duty cycle

powerful interrupt capabilities

Slide41

41

TPM Components

16-bit binary up

counter

driven by BUSCLK thru with programmable prescaler

8 choices: 1 .. 128

up to 8

channels

, ea. 16-bits, programmable for input capture (IC) or output compare (OC) operation

PWM generation capability

set of control/status registers

Slide42

TPM Block Diagram

Slide43

43

TPM Register Summary

RegisterNameNotesDescriptionFunctionTPMxSCTPM Status and Control Registerprimary status / control functions: clock source select, prescale factor select, timer overflow interrupt enableTPMxCNT1TPM Counter Register16-bit binary up counterTPMxMOD1TPM Counter Modulo Registersets modulo value for CNT counter registerTPMxCnSC2TPM Channel n Status / Control Registerper channel status/control functions: mode select, edge/level select, channel interrupt enableTPMxCnV1,2TPM Channel Value RegisterCNT value at Input Capture or Output Compare event

Notes:

1) are 16-bit registers but also support H/L-byte access

2) repeat for as many channels as available

Slide44

44

TPM Interrupts

InterruptLocal EnableSourceDescriptionTOFTOIE(TPMxSC)Timer overflowTimer Overflow interruptCHnFCHnIE(TPMxCnSC)Channel eventInput capture or output compare event occurred on channel n

Notes:

- each channel has its own interrupt vector

Slide45

implements full duplex, asynchronous serial communication at programmed baud rates with framing(MCF51JM ColdFire Ref. Manual, ch. 12)

SCI Module

Slide46

46

SCI Features

configurable baud rate

supports standard asynchronous rates

8- or 9-bit data format

for multi-node communications

receiver error detection

parity, noise, framing errors

10 interrupt events

although shared through 3 common vectors

uses pins on Ports C,E

most MCF members have multiple SCIs!

implements a total of 7 r/w registers

Slide47

47

SCI Components

13-bit baud rate

divider

determines data rate for both Tx & Rx

transmitter

w/ 11-bit PISO shift register

serializes output data to

TxD

with framing

parity generator

2 interrupt events shared on

SCI Transmit

vector

receiver

w/ 11-bit SIPO shift register

deserializes input data from

RxD

4 rx interrupt events on

SCI Receive

vector

4 error events on

SCI Error

vector

Slide48

48

SCI Transmitter Block Diagram

Slide49

49

SCI Receiver Block Diagram

Slide5
Recommended
View more...
We Need Your Support
Thank you for visiting our website and your interest in our free products and services. We are nonprofit website to share and download documents. To the running of this website, we need your help to support us.

Thanks to everyone for your continued support.

No, Thanks
SAVE OUR EARTH

We need your sign to support Project to invent "SMART AND CONTROLLABLE REFLECTIVE BALLOONS" to cover the Sun and Save Our Earth.

More details...

Sign Now!

We are very appreciated for your Prompt Action!

x