2-MHz clocked LCD drivers on glass

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2-MHz clocked LCD drivers on glass
  IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO 2 APRIL 1990 531 2-MHz Clocked LCD Drivers on Glass IGOR DE RYCKE, ANDRE VAN CALSTER, JAN VANFLETEREN, JOHAN DE BAETS, JAN DOUTRELOIGNE, HERBERT DE SMET, AND PETER VETTER Absstruct -In this paper a poly-CdSe thin-film transistor TIW) LCD driver circuit is described, which is integrated on the display itself, reduc- ing the interconnections o the display. The driver can be used to drive the rows as well as the columns of active and passive matrix LCD’s. Drivers made in a 25-pm technology operate at frequencies up to 2 MHz. Simulations indicate a maximum operating frequency of 8 MH2 for a 12.5 km technology. By using a time-multiplexing addressing scheme gray scales can be obtained. In order to address high-resolution displays with gray scales, parallel operating drivers can be used, requiring only one extra connection per parallel driver. I. INTRODUCTION grated drivers using a complementary poly-Si technology with shift registers operating at up to 2 MHz [9]. In this paper the performance of complete poly-CdSe drivers, consisting of shift registers, latches, and buffers, will be discussed. 11. DESIGN F DRIVER IRCUITS Poly-CdSe TFT’s are n-channel field-effect transistors; thus, TFT driver circuits can be derived from NMOS LSI circuits. The block diagram of the TFT driver is shown in Fig. 1 The driver consists of three parts: the shift register, the latch, and the buffer. ATRIX addressing schemes have become very pop- M lar in recently developed flat-panel displays. How- A. Inverter Des,gn ever, matrix addressing involves a large number of inter- connections between the display and the external driving circuits. Therefore it would be most attractive if the driver circuits could be placed directly on the display, in order to minimize the interconnection problem. An attractive way of doing so is integrating the driver circuits by thin-film transistor (TFT) processing on the display. As these driver circuits have to be able to handle video, only TFT pro- cesses based on polycrystalline semiconductors can be used. Commonly used polycrystalline TFT processes are the poly-Si technology and the poly-CdSe technology. Al- though the poly-Si process can rely on known IC pro- cesses, poly-CdSe is the only semiconductor that yields films with large carrier mobilities (50-160 cm2/V.s) on low-temperature glass, without any laser annealing steps. In the past poly-CdSe was claimed to be unstable and to have no standard processing. These problems have now been solved satisfactorily and a number of photolitho- graphic processes have been developed [1]-[4]. Integrated drivers using poly-Si and poly-CdSe have been published. Most of the designs are based on scanner circuits [5] (poly-CdSe), [6] (poly-Si), with operating frequencies of 500 kHz [6]. Other designs use a decoder-kbuffer for addressing the display columns and frequencies up to 1.25 MHz are reported [7], [8]. Still others reported on inte- Manuscript received January 17 1989; revised November 10, 1989. I. De Rycke and H. De Smet are supported by the IWONL. J. Doutreloigne is supported by the NFWO. The authors are with the Laboratory of Electronics, Ghent State University, B-9000 Ghent, Belgium. IEEE Log Number 8933722. From Fig. 1  it is seen that the complete driver circuit is based on inverters, and will work well if the basic inverter is designed properly. To design the inverter we followed the guidelines outlined by Elmasry [lo]. The characteristics of our n-channel TFT’s are as fol- lows. The dc output characteristics ZDs(VG,, VD, in the “linear” region of the TFT are described by [ll], [12] and where N, is the number of grain-boundary traps, Nb is the background doping of the CdSe film (in ~m-~), d is the dose of evaporated donors (in cm-*), t, is the semicon- ductor thickness, Cu is the oxide capacitance per unit area, pb is the electron mobility due to scattering at the grain boundaries, E, is the permittivity of the semiconduc- tor, and 4 is the elementary charge. From (1) it follows that the “linear” IDS( VG, character- istics (VD, small) are strongly nonlinearly dependent on V,,, especially at the onset of conduction (V,, ). This is due to the exponential influence of the grain barrier volt- age Vb. Only when V,, >> 0 does V, become neglectably 00lS-9200/90/0400-0531$01.00 01990 IEEE  532 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25 NO. 2 APRIL 1990 @l I sense 6 A amplifier TPLTP3 I 05 I buffer amplifier ’ 62 l %S+ vss-j=+ qip Fig. 1. Block diagram of the driver circuit. bs= v ld] t I I I* -10 5 5 10 VGsIVI (b) Fig. 2. IDS cs, VDs) characteristics of a poly-CdSe TFT: a) and (b) logarithmic. linear small and I,, become linearly dependent on VG,. We obtain We can define a limit transconductance: 4) Fig. 2 shows the dc output characteristics of a typical TFT (linear I,,( V,,) and log I,, VG,) plots), measured under ambient lighting conditions. The value of kp, im can be easily derived from the linear IDS(VGS) lot of Fig. 2: kp im equals the slope of the linear part of the curve (VGS > ). We measured that kp,lim varies between 2.5 and 5 pA/V2 depending on the oxide thickness to, and the semiconductor thckness t,. The geometrical ratio W/L varies between 1 and 25. The minimum value of L, Lmin, s either 12.5 or 25 pm in our process. Equation 3) and Fig. 2 show that the on-state dc-char- acteristics of a poly-CdSe TFT at V- >> can be approxi- mated by the known linear I,, VGs) haracteristics on an n-channel MOSFET (V,, << ): W I,, = ~hy V-., VT V,, = kp, im( VG, Gs. 5) The threshold voltage V, is determined by the intercept of the extrapolated linear part of the I,,(VG,) curve with the V,, axis. This approximation allows us to base our TFT circuits on MOSFET designs and use MOS simulation programs. These simulations will yield acceptable results, but will not give exact figures, due to the imperfection of the model. The actual onset of the drain current, marked V, in Fig. 2, differs from V, and is expressed [ll] by where N, equals 10” cmp2 and N, G 2 X lO”~m-~. uring the CdSe evaporation a controlled, small amount of In = 3 X 1014 cmp2) is added to the CdSe film. However, only a small fraction of these In atoms (Nd = 5 X 10” cm-’) act as donors. The threshold voltage V, derived from Fig. 2 is about 2-3 V larger than V, and is due to the presence of the already mentioned inter-grain potential barriers V,. The uncertainties on the donor concentrations are due to the difficulties of deriving these data for poly- crystalline films. However, this does not mean that V, cannot be processed in a reproducible way. In our case V = 0 for t, = 20 nm and V, = 2-3 V. The subthreshold currents are extremely low. For W/L = 1 the subthreshold current is only a few picoamperes. The transient characteristics of the TFT’s are deter- mined by the total capacitance CO t the output node. CO,, is equal to the parasitic output capacitance and the input gate capacitance of the loading stage. In order to minimize CO he self-aligned process published by Van Calster et al. [13] is used. The inverter used operates with a nonsaturated enhance- ment-type load. This type of inverter was chosen because it has good transient behavior, driver and load transistor are the same type (enhancement), the logic ONE goes to V,, (increased logic swing), and the fact that the inverter characteristics can be tuned to some extent by changing the gate voltage of the load TFT. In the case of an enhancement-load type of inverter, the load TFT is the smallest one and thus its geometrical ratio W/L equals 1, or W = L = Lmin. The geometrical ratio of the driver has to be sufficiently large, in order to obtain inverter characteristics with acceptable noise margins. On the other hand, the driver TFT may not become too large, because the input gate capacitance increases unnecessarily.  DE RYCKE et ai.: ~-MHZ LOCKED LCD DRIVERS ON GLASS 5 ___ --+--- $ bus I nafrix bus Fig. 3. Schematics of the driver. 0 io 20 ytv/ expenmen a1 calculafions ------- Fig. 4. Calculated and measured dc inverter characteristics. This has led us to a geometrical ratio of 15 for the driver TFT, or W=15 L- With this inverter layout as a basis, the layout of the driver circuit described in Fig. 1  is shown in Fig. 3.  The measured and calculated inverter characteristics are shown in Fig. 4.  The inverter delay T~ is entirely deter- mined by the time needed to charge the capacitance (input gate capacitance) of the loading stage. According to Elmasry [lo] the calculated T for our TFT inverter, with L,, = 25 pm, becomes 90 ns. Measured delays were 75-100 ns. From this discussion it is seen that poly-CdSe TFT's can be used easily in fast switching inverters, with predictable characteristics. B. Circuit Design and Functional Layout 1) Shift Register: The shift register is used to convert the serial input of video data into a parallel output, in order to drive each column of the display. This conversion leads to a drastic reduction in interconnections to the display: instead of connecting each column, only the serial input, the power supplies, and the clock lines must be connected. Although various types of shift registers can be realized with poly-CdSe TFT's, we preferred the dynamic two-phase clocked ratioed type with pass TFT's. The block diagram of this type of shift register is shown in the upper part of Fig. 1, the schematics in Fig. 3.  One bit consists of two pass TFT's, T,, and c4, nd two inverters, inverter I,,, formed by TFT's T,, and T,,,sd inverter Is2, formed by TFT's T5 nd q5. 0 nd ial are two nonoverlapping clocks and V,, is a dc power supply. The capacitances C,, and C,, of Fig. 1  are formed by the gate capacitances of the TFT's T,, and q5 The advantages of this dynamic, two-phase-clocked ratioed shift-register type are: a minimal number of transistors per stage (six TFT's); the output is a voltage instead of a charge stored on a capacitor, as in ratio-less types, which makes driving of the latch circuit less critical; no extra storage capacitors must be used; and only two clock lines are needed: the number of crossovers per stage is much less than in four-phase- clocked circuits. The disadvantages usually mentioned for this type of shift register are not important in our application. Power consumption is not very much different for our ratioed type than for ratio-less types, because the shift registers are driven near their maximum switching frequency. Space economy is not the main issue for the shift register: the width of a single bit stage is determined by the pitch of the pixels of the display, which is typically 300 pm. The most space-consuming part of the driver is the buffer amplifier, therefore the pixel pitch gives no restriction for the use of ratioed types of shift registers. The main disadvantage of our design of driver circuit is that when one bit of the shift register fails, all of the following bits (and thus all of the following columns or rows) fail. In order to maximize the yield, we opted for a shift-register design with a minimum number of crossovers and TFT's per stage. This has led us to the choice of a ratioed type two-phase-clocked dynamic shift register. 2) Latch: The latch circuit is wired as a sense amplifier used in NMOS dynamic memories. The sense amplifier retains the information present at the output of the shift register during the sensing pulse ia, high). The block diagram is shown in Fig. 1  The latch circuit is based on two cross-coupled inverters. This inverter combination has two stable states: a) Input of Ill = output of II2 high, output of Ill = nput of 112 ow. b) Input of I,, = output of II2 ow, output of Ill = input of II2 high. With closely matched inverters, when switching on the power supply of the inverters, each of these stable states has the same probability of occurring. An inverter is basically an amplifier with a gain < 1 Because of the positive feedback of the circuit, applying a small potential unbalance between points A and B of the circuit before switching power on will force the latch circuit into one state: V, < V, will force A low and B high, V, > V, will  534 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 2, APRIL 1990 force A high and B low. This principle is used for sensing the contents of the shft register. The schematics of sense amplifier are shown in Fig. 3.  While information is being shifted into the shift register, the sense amplifier is disconnected by means of the pass TFT’s Tpl and Tp2. n this way a line can be shifted in, while the sense and buffer amplifiers transfer the previous line onto the columns and pixels of the display. Because the sense amp and shift register are isolated from each other during the shifting, the sense amp forms almost no (capacitive) load for the shift register: Cof the pinched-off, self-aligned pass TFT Tpl is almost zero. So an impedance transformation of an almost zero capaci- tive load to the rather large capacitive load of the buffer amplifier is achieved with only two inverters. As previously mentioned, the switching of the sense amp is activated by a voltage difference between the input and reference voltage. When V differs from VIe by more than 1 V, switching occurs. This implies that a level shift from logic input levels to logic output levels can be introduced, simply by increasing the power supplies of the sense amp, leaving the power supply of the shift register at its nominal value. The sense amplifier not only retains the information present at the shift register but also restores the logic levels of this information. As the information stored in the shft register comes from inverters working at their speed limits and as the information can be distorted by, e.g., clock pulses, this restoring increases the noise margin of our circuit and also increases the maximum obtainable output swing of the buffer. Both the sensed input and its inverse are present at the output of the sense amplifier. So for driving a push-pull type of buffer, no extra inversion has to be done. All of these functions are accomplished with only two inverters and two pass TFT’s, which is much less than other suggested solutions, which use a number of buffer inverters followed by number of level-shifting inverters in order to drive a buffer-amplifier stage [6]. 3) Buffer Amplifier: Driving the large load of a column or a row of a display directly from the sense amplifier is not possible. The output levels of the sense amplifier are logic levels: they satisfy the conditions of V, and Vl being lower or higher, respectively, than a given threshold, but nothing is guaranteed about their specific analog value. This cannot be tolerated for driving the pixels of the display, so a buffer amplifier is needed. This buffer amplifier is a simple push-pull amplifier. This is a ratio-less type of device so charging and discharg- ing of the columns and rows of the display is done with the same time constant. Only one of the TFT’s is conducting at a time, so the output voltage is determined by the voltage of the power supplies. This implies a restriction on the output swing: the maximum obtainable output swing is Vl- V,, Vl and V, being the voltages of logic ONE and ZERO of the sense amp. Because the input capacitance of the buffer amp is mther large. the buffer is isolated from the sense amp Fig. 5. Suggested parallelism. during latch-up by means of the pass TFT’s Tp3 and Tp4 driven by clock D5. 4) Complete Driver: The total number of TFT’s in the complete driver is 16 per bit. It has the advantage that it is possible to use the same design for the row as well as for the column drivers. Both passive and active matrix dis- plays can be addressed: the level shifting capabilities of the sense amp allow large output swings in order to drive the gates of the pixel TFT’s of an active matrix, and the buffer amp allows precise control of the output voltage and thus of the voltage across the LC pixels. Because the LC reacts on the rms value of the voltage across the pixels, gray scales can be introduced using a time-multiplexing addressing scheme [ 141. In this scheme a frame consists of m subframes, with m being the number of gray scale bits we want to display. In each subframe one bit is displayed with the appropriate V,,, and Ks- n order to obtain the desired gray level. In ths way 2“ gray levels can be obtained. Ths addressing scheme implies that a whole frame must be stored in memory and one gray-level bit must be read at a time, and that the driver circuit must operate at a frequency m times the non-gray- scale one. When the dimensions or gray scales of the display require an operating frequency higher than the maximum shifting frequency of the shift register, the driver circuit can be subdivided as shown in Fig. 5. The video data for the subdrivers must be supplied in parallel. Because all of the subdrivers share the same clocking lines and power supplies, only extra data input lines are added. This ar- rangement demands that the information of a whole line is preprocessed. 111. MEASUREMENTS ND OPERATION OF THE DRIVER IRCUIT The first realized drivers were processed with our 25-pm technology. Although these drivers operate at frequencies up to 2 MHz, “in circuit” measurements could not be made at these hgh frequencies because the capacitive loading of the measure probe distorted the measurement. At a shfting frequency of 2 MHz only the output of the  DE RYCKE et ul.: ~-MHZ CLOCKED LCD DRIVERS ON GLASS 535 l 0 3 l  0 l;::III:: LO 80 1zO 160 / p) Measured output of shift register. ig. 6. buffer amplifier could be mkasured accurately, confirming that the circuit operated correctly at this frequency. There- fore the figures shown are from n circuit measurements, made at a much lower frequency of 42 kHz. The power supply V,, = 10 V, V,, = 20 V, ye = 2.5 V, the high level of the clocks Ql 1 2, Q5 equals 16 V, and the low level is -4 V. Q4 switches between V,, and 0 V. Video information is shifted synchronous with clock al. Fig. 6 shows Ql he input and the output of the shift-reg- ister bits 1, 2, and 3. Only when Ql s high are the inverters of the shift register active, so during sensing Q, should stay high. Before connecting the latch to the shift register it is discharged by putting D4 high. Both output nodes of the sense amplifier then have the same voltage equal to V,,. The latch is connected to the shift register by putting Q2 high and then the latch is activated: Q4 goes to ground potential. In this phase the latch switches to one of its two stable states and it may be isolated from the shift register a2 oes low). The switching of the latch is controlled by the overlap of Q4 going to ground potential and Q2 going low. We measured that this overlap should not be less than 400 ns (this minimum overlap was measured by verifying the buffer output and with no probe loading of the sense amp at a 2-MHz clocking frequency of the shift register). This means that sensing of the shift register can be done in about one bit delay. Because sensing of the shift register only occurs once a line, this puts no restriction on the speed of the driver circuit: the time needed to accept a full line of video data will almost equal the time needed to shift the information into the shift register. Fig. 7  shows the outputs of the latches connected to bits 1, 2, and 3 of the shift register (whose outputs are shown in Fig. 6). The sensing pulse Q2 and the power-switching pulse Q4 occur in the time interval t = 80-110 ps. From Fig. 7, it is seen that the logic output levels of the latches are V, = 2 V and V, = 10 V. The maximum output 01' 20- 0 I vL ATcHk   V~~~~~ 3 l:Lw LO 80 120 160 t ysl Fig. 7. Measured output of latch. Gu   L 8 12 16 / Imsj cl Fig. 8. Measured outputs of buffer amplifiers. swing of the buffer will be 8 V. This is too small for driving the gate lines of an active matrix but is sufficient for driving a passive display. For driving the gate lines of an active matrix, level shifting as presented in the above section must be done. The outputs of the buffer stages 1, 2, and 3 (connected to the outputs of the latches of Fig. 7) are shown in Fig. 8.  These outputs can be used for driving a passive display with V,,, equal to a square wave with an amplitude of 2.5 V and a dc offset of 8 V and V,,- equal to 8 V and the back electrode of the pixel connected to ys-. or an OFF pixel, shown in Fig. 8(a), the output of the buffer amplifier equals V,,- = Vback nd the liquid crystal does not switch. An ON pixel, shown in Fig. 8(b), means that the buffer output equals y, , which is sufficient to switch the LC. Because V,,, is a square wave centered around V,,-, there is no dc component across the LC. For driving active matrices V,,, and Ks- must be dc voltages, yet a dc component across the LC can be pre- vented by connecting the backplane of the display alter- nately to the voltages V,,, and y,- in consecutive frames.
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