10.1109@ICPEICES.2016.7853184 | Power Inverter | Power Electronics

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  1st IEEE Inernaional Conference on Power Elecronic, Inelligen Conrol and Energy Syem (ICPEICES-2016) A Seven Level Multilevel Inverter Topology with Improved Results using PWM Technique Vy Go, Jgds Kumr2 d Jm Gmbr3 1,2,3Depaent ofElectrical Engg. PEC University ofTechnology Chandigah India Absaet-  The new emerging multi level inverer topologies with reduced device count, beter control strategies improved modulation schemes and capability to address various operational issues have proved to be highly superior to that of two level inverers and the conventional multilevel inverter topologies. This paper presents signicantly improved results of an existing 6 sitches and  DC sources multilevel inverer topology to produce great perfection in the seven level output voltage waveform. The major impact of the improved results is the reduction in total harmoni distortion (THD). The control methodology employed is Level Shied PWM technique based on which the topology is simulated for Phase Opposition Disposition  Alternate Phase Opposition Disposition and Alternate Phase Opposition Disposition + Variable Frequency modulation techniques. Multilevel Inverters today present a viable solution for high dynami performance and power quality seeking appliations ultimately focusing to achieve almost perfect sinusoidal output voltage with minimum harmoni content. Thus in this paper an effort is made to reduce the THD in the output voltage waveform. An analysis is done and a comparison is also made between the existing results and the new results obtained. These results are veried using MATLAB/SIMULINK and the analysis of harmoni spectrum is done through the Fast Fourier transform  window. Kywords-Multlvl Invrt; N Topologis; Total Harmonie Distoron; Ll Shtd Mulearrir PW Tehniqus I. NTRODTION The Conventional cascaded seven level m  ulti level nverters utilize tree DC sources and twelve switches [][6]. Many compaisons have been made by various authors between the diode camped ying capacitor and  the cascaded H-bridge MLI [7]-[8]. The man disadvantage n these structes is that for higher levels of  the output voltage higher number of power switches is  requred. Hence improvement is requred to lower the no. of switches of the inverter. This topology utilizes four DC sources and six switches and it produces the output voltage waveform with signicantly less harmonics as compared to conventional cascaded multilevel inverter [9]. The ndamental concept of an MLI to generate nea to sinusoidal output voltage waveform is by using power electronic switches like IGBTs MOSFETs etc. along with appropriate DC voltage sour ces to perform the power conversion i.e. the DC to AC conversion. Capacitors batteries and renewable energy voltage soces can be  used as the multiple nput DC sources. Snce the batteries 978-1-4673-8587-9/16/$31.00 ©2016 IEEE [1)  must be isolated om the semiconductor switches and the other H-bridges hence a sepate maxmm power point  ackng (MPPT) chage conoller is requred to chage its storage batteries ndependently. Hence a PV system  that uses the cascaded H-bridge multilevel inverter  topology can be quite bulk and costly. Moreover due to  the ntermitent nate ofthe renewable energy sources the  performance and eciency ofthe mutilevel inverter may deteriorate. For this the output voltage quality ofthe MLI is mproved as the number of output voltage level ncrease reachng to that ofthe perfect sinusoid. Also the quantity and size of output lters can be reduced because of the reduction n the lower order hamonics content in  the output votage waveform. O  the other hand with lesser number of levels they need lage sized as wel as expensive LC output lters. A multilevel inverter offers various advantages over a conventional two level inverter by employing a high switchng equency PM which not only produces the output votage with lower hamonic distortion but also reduces dv/dt sesses thereby  reducng elecomagnetic compatibility (EMC) problems  these advantages will be elaborated later in this paper. Since hamonics play a major role n context of power electronics ther reduction is the primary motive in this  paper so that the multilevel inverter topology can be applied to various high power quality seeking applications. To be knon as a multilevel inverter each  phase ofthe inverter should produce at least tree dierent voltages and this dierentiates the conventional two-evel voltage source nverter (L-VSI) om the multilevel family. In this paper the crcuit is checked out using level shied multicarier PWM teciques [0]. Then identiing the effectiveness by workng the simulated circuit with In-Phase Disposition (PD) Phase Opposition Disposition (POD) Alteate Phase Opposition Disposition (APOD) PM modulation schemes []-[]  usng M TLAB/SIMLINK.  OPOLOGIES A Canventianl Tapa/a Cascaded H-Bridge multilevel inverters ae obtaned by connectng n series more than two single phase HBridge nverters each consistng of 4 switches hence the  name []-[4]. In general terms when conectng k HBridges n series k+  dierent voltage levels are obtaned and maxim output voltage kVã Thus for a seven level inverter it uses  H-Bridges n series hence a  1st IEEE Inernaional Conference on Power Elecronic, Inelligen Conrol and Energy Syem (ICPEICES-2016)  total of  switches and maxmum output votage ofVdc. It is important to note that the two switches connected n  the same leg must not conduct at the same tme n order to  prevent a complete short crcuit. Fig.  represents the Conventional Cascaded H bridge nverter. Vdel VdeZ V d c  Fig. I: ascaded H- bridge Structure for Seven- evel MultilevelInverter B  Level 6 Switch Tapala This topology uses 4 dc votage sour ces and 6 switches as shon in Fig. . Switches S S S are  utilized for producng levels while switches S4 S5 ae  utilized for reversing the polarity [5]. The switch S6 is connected across the load for obtanng zero level. Table   represents its switchng sequence. In this topology the  nber of switches and percentage of T produced is  much lesser as compaed to the conventional and other existng 9 switch 7 switch topologies.  switches conduct n the positive half cycle and two switches conduct for the  negative half cycle and one switch for generatng zero level. Here level shing PWM tecnique is used.  Fig. 2: Seven Level 6 Switch MultilevelInverter Topology [ T ABLE I: WICHING AES OF 6-WICH 4   OURCE TOPOLOGY Sr. No. S] S2 S3 S S S6 Vo 1 0 0 I 0 I 0  Vdc  2. 0 I 0 0 I 0  2Vdc  3. I 0 0 0 I 0  3Vdc 4 0 0 0 0 0 I 0 5 I 0 0 I 0 0 - Vdc 6. 0 I 0 I 0 0 - 2Vdc 7. 0 0 I I 0 0 - 3Vdc  Where, refers to OFF; I  refers to ON. III. ETHOOLOGY SE In ode o ealie he muilevel invee opology a  paticula conol sategy needs to be used. There are  many controllng schemes n literate; one ofthese is the  modulation tecnique that can be cassied based on the switchng equency. These include: ndamental switchng equency where each nverter n one cycle  undergoes one commutation e.g. Selective Harmonic Elmnation (S) Space Vector Conol (SVC) and  Nearest Votage Level Conol (NVLC) and high switchng equency modulation tecnique where n one cycle the nverter dergoes several commutations e.g. PM tecnique and Space Vector Modulation (SVM). One of the simplest methods of obtanng votage source modulation is tough intersectng a modulatng signal which is mostly a sne wave with i angular carrier waveform. This scheme is explaned as n carrier based PM technique [6]. Muticarrier P Tecniques can be categorized in two groups i.e.; Level Shied methods (LS) and Phase Shied (PS) P methods [7] latter  produces higher amot of total harmonic distortion as compared to former. Therefore Level Shied P  tecnique is considered [8]. Level shing tecnique is rther categorized nto  tree techniques which are: In-Phase Disposition (PD) Phase Opposition Disposition (POD) and Alteate Phase Opposition Disposition (APOD) [9]-[0]. hen usng level shied P tecnique an 'N level inverter uses 'N- carrier waves such that the 'N- iangular caiers ae vertically displaced and the bands they occupy are equally spaced. Moreover along with the vertical displacement there is also phase reversal between the  i angula cariers. In-Phase Disposition (PD) nvolves all  the carriers n phase [] which when compaed with the sinusoidal reference produce the desred pulses. Appropriate comparisons ae made and accordng to the desired pulse pate the logical crcuits are used. The  pulses thus obtaned ae fed to the power electronic switch n this case MOSFET and the desred seven level output votage waveform is obtained. In this paper for e.g. n order to obtan V votage level switches S and S5 should be ON thus we now  know the desired pulse patte. To achieve this patte comparisons ae made between the snusoidal reference and the iangula cariers and if desired additional logical circuits can be used.  1st IEEE Inernaional Conference on Power Elecronic, Inelligen Conrol and Energy Syem (ICPEICES-2016) Here the same topology is simulated for POD APOD and APOD+VF modulation tecnique and the desred seven level output votage waveform is obtaned. In the case of Phase Opposition Disposition (POD) [] as shon in Fig.  all the iangular carriers above zero reference are n same phase whereas those below zero  reference ae 80 degrees out ofphase. 1 I I  � C E ' 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 tm  Fig. 3: POD PWM Technique Each carier is 80 degrees in phase dierence with its neighborng carier n Alteate Phase Opposition Disposition (APOD) as shon n Fig. 4. I   C E ' 1  Fig. 4:  APOD PWM Technique In APOD+VF tecnique each carier wave is displaced to its adjacent carrier wave by 80 degrees [][4] such that the carrier equency ofthe lower most and  the uppermost carier waves is appropriately increased as shon n Fig. 5. [  � C E ' 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 tm  Fig. 5:  APOD+VF PWM Technique IV. IMULATION SULTS The above discussed 7 level 6 switch topology is simulated based on the POD APOD APOD+VF P  tecnique and the hamoni spectr is analyzed using MTLAB/ Simulnk. The aplitude of the dc source is taken as V and load resistance is 0 oms. MOSFET block paraeters are as folows: FET resistance= .ohms Inteal Diode Resistance =kilo oms The resuts we obtained ae shon n Fig. 6 Fig. 7 and Fig. 8. Selected ig na l:  y les.  w indo  (in red):  cles : r    l      002 004 005 008 0 T \ -T analysis  - r c C E r c    -  >   ' r  Fundam en tal 5 Hz   = 27  ã THD= 577 % 00 0 50 40 20 0 _ . . J 0 00 400 500 00 Fequenc  Hz)  Fig. 6: FFT Analysis of7- Level 6-Switch Topology using  POD PWM Technique  000  1st IEEE Inernaional Conference on Power Elecronic, Inelligen Conrol and Energy Syem (ICPEICES-2016) Selected signal: 5 y les. FF  wndo w (in red) 3 yles : r \ 7  1     o 00 00 4 006 00 01  ( -T analysis  - Fundamental 0Hz) = 28 , HD= 146 % 100    C 80 E  60 § L 40 � ' 0  : J _ . . _I  00 00 600 800 1000 Frequency (Hz)  Fig. 7: FFT Analysis of7- Leve6-Switch Topology using APOD PWM  Technique Selected signal 5 y es FF  win o w (in red) 3 y les J \  \17   o 002 0.04 006 008 01 T ( T analysis   undamenal 0Hz)  3046 , TD 10.35  00 �   0 � 60 §  - 40   ' 0 � I .     200 400 600 00 1000 Frequeny (Hz)  Fig. 8: FFT Analysis of7- Leve6-Switch Topology using APOD+VF  PWM Technique V. COMPSON OF SUL  TS  T  ABLE  2: OMPARISON OF  THD OF EVEN EVEL IX WICH TOPOLOGY BEWEEN XISlNG SULS AND ROPOSED SULS Sr. Topology Existing Proposed No. Results% Results% THD 2 THD I Seven level six switch topology 18.25% 16.77%  with 4 D  source using Phase  Opposition Disposition PWM  technique  2. Seven level six switch topology 16.48% 14.61%  with 4 D  source using lternate  Phase Opposition Disposition  PWM technique  3. Seven level six switch topology 10.35%  with 4 D  source using lternate  Phase Opposition Disposition +  Variable Frequency PWM  technique [4 Based on the above simulation results it can be seen  that the percentage T obtaned n the seven-evel  multilevel nverter topology is lesser than that of the  results given n the reference [5]. A detailed compaison is made based on the above T analysis for POD APOD and APOD+VF  modulation tecnique as shon n Table . A comparison of the T of the obtaned results and various other existng multilevel inverter topologies are shon n Table . TABLE  3: ERCENAGE  THD OMPARISON OF IFFEEN TOPOLOGIES PWM Technique PD POD APOD APOD+VF ascaded 7 - level  24.26 23.13 22.46 -7 level 9 switch - 20.52 --7 level 7 switch symmetrical -18.15 --7 level 7 switch asymmetrical -15.79 --7 level 6 switch 4 dc source -16.77 14.76 10.35 7 level 6 switch 3 dc source -15.91 --7 level 6 switch asymmetrical -18.69 -- Thus it can be seen om Table  that the proposed  results ae better than the existng results such that for Phase Opposition Disposition P tecnique the  percentage T in the existng results is 8.5% and that n the proposed results is 6.77% for Alteate Phase Opposition Disposition P tecnique the percentage T in the existng results is 6.48% and that in the  proposed results is 4.6%. Hence the proposed results ae signicantly better than the existng results. Moreover n the reference [5] the topology is not simulated for Alteate Phase Opposition Disposition + Variable Frequency P tecnique but n this paper the topology is simulated for this P technique and the percentage T thus obtaned is 0.5%. Hence it is worth  mentionng that the percentage T is mnimum for Alteate Phase Opposition Disposition + Variable Frequency P technique which n the case of  multilevel nverters is a signicantly good result. The multilevel approach for DC to AC conversion offers many advantages such as: ã The starcase waveform not only ehibits an improved hamoni prole but also the dv/dt stresses are greatly reduced. Thus mnmizng  the lter size or even elimnatng lter  requrement and at the sae tme electromagnetic compatibility problems can be adessed. ã MLI produces much lesser sess n the bearng of a motor because the common mode voltage  produced is much smaller when the motor is used n a multilevel motor ive application ã Renewable energy sources such as sola PV cells wind energy and el cells can be readily ncorporated n the multilevel converter  tecnology and the nput sources can be controlled for equal load shang.
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